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Add support for enumeration types.
2009-03-05
Matthijs Kooijman
Strip adjacent underscores from VHDLIds.
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2009-03-04
Matthijs Kooijman
Provide preliminary support for list types.
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2009-03-04
Matthijs Kooijman
Add some hardware models using vectors (FSVec).
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2009-03-04
Matthijs Kooijman
Fix propagateState removing all non-FApp SigDefs.
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2009-03-04
Matthijs Kooijman
Map the clk port on stateful function applications.
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2009-03-04
Matthijs Kooijman
Don't inline alu.
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2009-03-04
Matthijs Kooijman
Remove support for DontCare.
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2009-03-03
Matthijs Kooijman
Fill in propagateState.
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2009-03-03
Matthijs Kooijman
Remove the now obsolete getOwnStates.
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2009-03-03
Matthijs Kooijman
Add some predicates and accessors to FlattenTypes.
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2009-03-03
Matthijs Kooijman
Let VHDL use SignalInfo instead of HsFunction for generating...
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2009-03-03
Matthijs Kooijman
Add initial (dummy) propagateState function.
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2009-03-03
Matthijs Kooijman
Add vim modeline.
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2009-03-03
Matthijs Kooijman
Add a is_FApp predicate.
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2009-03-03
Matthijs Kooijman
Never inline the half_adder function.
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2009-03-03
Matthijs Kooijman
Add StandalonDeriving language option to Pretty.
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2009-03-03
Matthijs Kooijman
Don't add duplicate name hints.
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2009-03-03
Matthijs Kooijman
Put VHDL files for each design in a separate directory.
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2009-03-03
Matthijs Kooijman
Allow for generating VHDL for stateless functions.
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2009-02-27
Matthijs Kooijman
Add some newlines in the output.
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2009-02-27
Matthijs Kooijman
Make exec have a single binding.
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2009-02-27
Matthijs Kooijman
Add a two-port mux hardware model.
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2009-02-19
Matthijs Kooijman
Write each VHDL entity to a seperate file.
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2009-02-19
Matthijs Kooijman
Let the exec function output something.
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2009-02-19
Matthijs Kooijman
Support construction of empty tuples.
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2009-02-19
Matthijs Kooijman
Print the list of signals sorted by id.
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2009-02-19
Matthijs Kooijman
Also allow uppercase letters and a period in VHDL ids.
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2009-02-19
Matthijs Kooijman
Add name hints to various signals generated.
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2009-02-19
Matthijs Kooijman
Strip invalid characters from VHDL identifiers.
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2009-02-19
Matthijs Kooijman
Use the name hints in signal name construction.
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2009-02-19
Matthijs Kooijman
Do the naming of a signal in named function instead...
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2009-02-19
Matthijs Kooijman
Allow name hints to be set for a signal.
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2009-02-19
Matthijs Kooijman
Enable the DontCare value for Bit again.
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2009-02-19
Matthijs Kooijman
Print the Defs list sorted.
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2009-02-19
Matthijs Kooijman
Make register_bank work, with a bunch of changes.
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2009-02-19
Matthijs Kooijman
Let zipValueMapsWith show the trees in the error.
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2009-02-19
Matthijs Kooijman
Use tuples instead of a ADT for the register bank state.
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2009-02-19
Matthijs Kooijman
Add space in error message.
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2009-02-19
Matthijs Kooijman
Make listBind also show a pretty printed output.
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2009-02-19
Matthijs Kooijman
Further reduce main and add a makeVHDL function.
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2009-02-19
Matthijs Kooijman
Support multiple alternative case expressions.
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2009-02-19
Matthijs Kooijman
Add stateful alu (with empty state).
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2009-02-18
Matthijs Kooijman
Add a simple four-bit shift register model.
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2009-02-18
Matthijs Kooijman
Use a different approach for marking SigUses.
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2009-02-18
Matthijs Kooijman
Add setSignalInfo accessor for FlattenState.
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2009-02-18
Matthijs Kooijman
Generate VHDL for UncondDefs.
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2009-02-18
Matthijs Kooijman
Add a getSignalInfo accessor.
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2009-02-18
Matthijs Kooijman
Add a listBind function to show the Core for a bind.
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2009-02-18
Matthijs Kooijman
Split out the large main function a bit.
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2009-02-18
Matthijs Kooijman
Remove the DontCare value from the Bit type.
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2009-02-18
Matthijs Kooijman
Derive and use show instead of ppr to display Exprs.
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2009-02-18
Matthijs Kooijman
Fix comment indent.
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2009-02-17
Matthijs Kooijman
Generalize FApp and CondDef into SigDef and add UncondDef.
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2009-02-17
Matthijs Kooijman
Add a type alias StateId for state numbers.
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2009-02-17
Matthijs Kooijman
Remove type parameterisation of SignalMap.
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2009-02-17
Matthijs Kooijman
Don't generate ports for non-port signals.
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2009-02-17
Matthijs Kooijman
Generate VHDL signals for internal signals and state.
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2009-02-17
Matthijs Kooijman
Add predicates for SigUse.
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2009-02-17
Matthijs Kooijman
Mark all signals as ports or states when appropriate.
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2009-02-17
Matthijs Kooijman
Always import IEEE.std_logic_1164 in the generated...
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2009-02-17
Matthijs Kooijman
Move the DesignFile creation to VHDL.
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2009-02-17
Matthijs Kooijman
Add clk port on any stateful entity.
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2009-02-17
Matthijs Kooijman
Create state procs for state signals.
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2009-02-16
Matthijs Kooijman
Mark port signals as such during flattening.
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2009-02-16
Matthijs Kooijman
Improve the pretty output of the signal list.
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2009-02-16
Matthijs Kooijman
Make the pretty output more pretty.
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2009-02-16
Matthijs Kooijman
Reduce genSignals to a single line using Traversable.
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2009-02-16
Matthijs Kooijman
Store a use for each signal in a flattened function.
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2009-02-16
Matthijs Kooijman
Add port maps to component instantiations.
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2009-02-16
Matthijs Kooijman
Make application names unique.
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2009-02-16
Matthijs Kooijman
Add Entities for builtin functions.
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2009-02-16
Matthijs Kooijman
Let mkCompInsSm look up the actual VHDL entity id.
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2009-02-16
Matthijs Kooijman
Put mkCompInsSm in the VHDLState monad.
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2009-02-13
Matthijs Kooijman
Make modFuncs work with stateful functions.
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2009-02-13
Matthijs Kooijman
Generalize some session modification functions.
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2009-02-13
Matthijs Kooijman
Generate dummy component instantiations for each architecture.
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2009-02-13
Matthijs Kooijman
Move some pretty printing code around.
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2009-02-13
Matthijs Kooijman
Use less general names as labels some fields.
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2009-02-13
Matthijs Kooijman
Generate a VHDL architecture for each function.
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2009-02-13
Matthijs Kooijman
Add port declarations to the VHDL entities.
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2009-02-13
Matthijs Kooijman
Put a TypeMark in a VHDLSignalmap.
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2009-02-13
Matthijs Kooijman
Rename fields of SignalInfo.
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2009-02-13
Matthijs Kooijman
Store the Haskell Type in SignalInfo.
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2009-02-13
Matthijs Kooijman
Add the VHDLTypes module
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2009-02-13
Matthijs Kooijman
Extract entities from the session and return them in...
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2009-02-13
Matthijs Kooijman
Generate VHDL entity declarations.
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2009-02-13
Matthijs Kooijman
Create an entity for each function.
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2009-02-13
Matthijs Kooijman
Store signals in a map.
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2009-02-13
Matthijs Kooijman
Name signals in a function after flattening it.
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2009-02-13
Matthijs Kooijman
Add a modFunc function to edit a function in the session.
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2009-02-13
Matthijs Kooijman
Remove NamedFlatFunction again.
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2009-02-11
Matthijs Kooijman
Allow a FlatFunction to be named as well as unnamed.
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2009-02-11
Matthijs Kooijman
Fill the signal list in FlatFunction.
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2009-02-11
Matthijs Kooijman
Add a list of used signals to FlatFunction.
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2009-02-11
Matthijs Kooijman
Remove the distinction between SignalDef and SignalUse.
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2009-02-11
Matthijs Kooijman
Make FlatFunction parameterized with the signal id...
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2009-02-11
Matthijs Kooijman
Move around a bunch of types.
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2009-02-11
Matthijs Kooijman
Add more builtin functions.
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2009-02-11
Matthijs Kooijman
Only force a stateful interface for top level functions.
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2009-02-11
Matthijs Kooijman
Add facilities for builtin functions.
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