Move the DesignFile creation to VHDL.

diff --git a/Translator.hs b/Translator.hs
index c037a1e24a0d30a8f97aeca69c815fa65ad9e97d..9cced3444d452607e3b8d35cc9b3ce631b6ee515 100644 (file)
--- a/Translator.hs
+++ b/Translator.hs
@@ -72,13 +72,7 @@ main =
       modFuncs nameFlatFunction
       modFuncs VHDL.createEntity
       modFuncs VHDL.createArchitecture
-      -- Extract the library units generated from all the functions in the
-      -- session.
-      funcs <- getFuncs
-      let units = concat $ map VHDL.getLibraryUnits funcs
-      return $ AST.DesignFile 
-        []
-        units
+      VHDL.getDesignFile
 
 findBind :: [CoreBind] -> String -> Maybe CoreBind
 findBind binds lookfor =

diff --git a/VHDL.hs b/VHDL.hs
index ee61c500a6916f676fd75e1c7566d6d8bb868eab..5d57bb574c98fe55f51e041306e42ccabfcf6950 100644 (file)
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -20,6 +20,16 @@ import FlattenTypes
 import TranslatorTypes
 import Pretty
 
+getDesignFile :: VHDLState AST.DesignFile
+getDesignFile = do
+  -- Extract the library units generated from all the functions in the
+  -- session.
+  funcs <- getFuncs
+  let units = concat $ map getLibraryUnits funcs
+  return $ AST.DesignFile 
+    []
+    units
+  
 -- | Create an entity for a given function
 createEntity ::
   HsFunction        -- | The function signature