Generate VHDL entity declarations.
authorMatthijs Kooijman <m.kooijman@student.utwente.nl>
Fri, 13 Feb 2009 11:28:36 +0000 (12:28 +0100)
committerMatthijs Kooijman <m.kooijman@student.utwente.nl>
Fri, 13 Feb 2009 11:28:36 +0000 (12:28 +0100)
commitd347b7fdac3421817da5d1f571c0837fdbd28127
tree9d5f9813280ca19a78a9fee7d0554086999b36c8
parentfcd5e88b1c14a3129253de9e8c225e3b13e041e7
Generate VHDL entity declarations.

These declarations are still without ports and with a name that might not
be unique, though.
VHDL.hs