Add a simple four-bit shift register model.
authorMatthijs Kooijman <m.kooijman@student.utwente.nl>
Wed, 18 Feb 2009 19:27:20 +0000 (20:27 +0100)
committerMatthijs Kooijman <m.kooijman@student.utwente.nl>
Wed, 18 Feb 2009 19:27:20 +0000 (20:27 +0100)
commit0082f01a853476cdcec0e73bacf8c0d4508dbec0
tree355c3d9e905844070ab8dacbd2dcdbc19c249e58
parent5b7046a2981a1e65483527cab15314dd140e0002
Add a simple four-bit shift register model.

This model is already translatable to VHDL.
Adders.hs
Translator.hs