From 0082f01a853476cdcec0e73bacf8c0d4508dbec0 Mon Sep 17 00:00:00 2001 From: Matthijs Kooijman Date: Wed, 18 Feb 2009 20:27:20 +0100 Subject: [PATCH] Add a simple four-bit shift register model. This model is already translatable to VHDL. --- Adders.hs | 8 ++++++++ Translator.hs | 2 +- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/Adders.hs b/Adders.hs index ce26166..ac93a33 100644 --- a/Adders.hs +++ b/Adders.hs @@ -39,6 +39,14 @@ dff d s = (s', q) q = s s' = d +type ShifterState = (Bit, Bit, Bit, Bit) +shifter :: Bit -> ShifterState -> (ShifterState, Bit) +shifter a s = + (s', o) + where + s' = (a, b, c, d) + (b, c, d, o) = s + -- Combinatoric stateless no-carry adder -- A -> B -> S no_carry_adder :: (Bit, Bit) -> Bit diff --git a/Translator.hs b/Translator.hs index c16406b..cf2fb96 100644 --- a/Translator.hs +++ b/Translator.hs @@ -45,7 +45,7 @@ main = do -- Load the module core <- loadModule "Adders.hs" -- Translate to VHDL - vhdl <- moduleToVHDL core ["dff"] + vhdl <- moduleToVHDL core ["shifter"] -- Write VHDL to file writeVHDL vhdl "../vhdl/vhdl/output.vhdl" -- 2.30.2