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Split off the VHDL type generating code.
[matthijs/master-project/cλash.git]
/
VHDL.hs
2009-06-21
Matthijs Kooijman
Split off the VHDL type generating code.
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2009-06-19
Christiaan Baaij
Merge branch 'cλash' of git.stderr.nl/matthijs/projects...
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2009-06-19
Christiaan Baaij
Added function calls
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2009-06-19
Matthijs Kooijman
Support VHDL generation for two-alternative cases.
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2009-06-19
Christiaan Baaij
Merge branch 'cλash' of git.stderr.nl/matthijs/projects...
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2009-06-19
Christiaan Baaij
Started adding builtin functions
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2009-06-19
Christiaan Baaij
Cabalized clash
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2009-06-15
Matthijs Kooijman
Generate VHDL from Core instead of flat functions.
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2009-04-14
Matthijs Kooijman
Generate VHDL typecasts for literals when needed.
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2009-04-14
Matthijs Kooijman
Put mkConcSm inside the VHDLState monad.
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2009-04-14
Matthijs Kooijman
Add a Type to a Literal SignalExpr.
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2009-04-09
Matthijs Kooijman
Generalize VHDL type creation for SizedWord and FSVec.
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2009-04-09
Matthijs Kooijman
Add (non-working) support for SizedWord literals.
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2009-04-09
Matthijs Kooijman
Translate the SizedWord type to a VHDL vector.
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2009-04-06
Matthijs Kooijman
Use basic identifiers for builtins.
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2009-04-06
Matthijs Kooijman
Use extended VHDL identifiers where possible.
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2009-04-06
Matthijs Kooijman
Use the actual FSVec length to create VHDL vectors.
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2009-04-06
Matthijs Kooijman
Cleanup imports and add a vim modeline.
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2009-03-10
Matthijs Kooijman
Add a TODO.
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2009-03-10
Matthijs Kooijman
Remove a few stale TODOs.
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2009-03-10
Matthijs Kooijman
Import the ieee library into the generated types package.
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2009-03-10
Matthijs Kooijman
Filter out dots from generated type id's.
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2009-03-10
Matthijs Kooijman
Put vhdl_ty in the (new) TypeState Monad.
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2009-03-10
Matthijs Kooijman
Output a package containing all type declarations.
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2009-03-10
Matthijs Kooijman
Add support for builtin functions again.
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2009-03-10
Matthijs Kooijman
Redo the global (state) structure of the translator.
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2009-03-09
Matthijs Kooijman
Use Data.Accessor for FuncData.
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2009-03-09
Matthijs Kooijman
Remove createArchitecture from the VHDLState Monad.
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2009-03-09
Matthijs Kooijman
Remove mkConcSm from the VHDLState monad.
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2009-03-09
Matthijs Kooijman
Make createEntity preserve the Entity on builtin functions.
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2009-03-05
Matthijs Kooijman
Remove createEntity from the VHDLState monad.
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2009-03-05
Matthijs Kooijman
Remove getDesignFiles from the VHDLState monad.
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2009-03-05
Matthijs Kooijman
Strip adjacent underscores from VHDLIds.
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2009-03-04
Matthijs Kooijman
Provide preliminary support for list types.
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2009-03-04
Matthijs Kooijman
Map the clk port on stateful function applications.
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2009-03-03
Matthijs Kooijman
Let VHDL use SignalInfo instead of HsFunction for gener...
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2009-02-19
Matthijs Kooijman
Write each VHDL entity to a seperate file.
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2009-02-19
Matthijs Kooijman
Also allow uppercase letters and a period in VHDL ids.
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2009-02-19
Matthijs Kooijman
Strip invalid characters from VHDL identifiers.
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2009-02-19
Matthijs Kooijman
Enable the DontCare value for Bit again.
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2009-02-19
Matthijs Kooijman
Make register_bank work, with a bunch of changes.
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2009-02-19
Matthijs Kooijman
Support multiple alternative case expressions.
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2009-02-18
Matthijs Kooijman
Generate VHDL for UncondDefs.
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2009-02-17
Matthijs Kooijman
Generalize FApp and CondDef into SigDef and add UncondDef.
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2009-02-17
Matthijs Kooijman
Add a type alias StateId for state numbers.
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2009-02-17
Matthijs Kooijman
Remove type parameterisation of SignalMap.
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2009-02-17
Matthijs Kooijman
Don't generate ports for non-port signals.
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2009-02-17
Matthijs Kooijman
Generate VHDL signals for internal signals and state.
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2009-02-17
Matthijs Kooijman
Always import IEEE.std_logic_1164 in the generated...
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2009-02-17
Matthijs Kooijman
Move the DesignFile creation to VHDL.
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2009-02-17
Matthijs Kooijman
Add clk port on any stateful entity.
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2009-02-17
Matthijs Kooijman
Create state procs for state signals.
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2009-02-16
Matthijs Kooijman
Add port maps to component instantiations.
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2009-02-16
Matthijs Kooijman
Make application names unique.
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2009-02-16
Matthijs Kooijman
Let mkCompInsSm look up the actual VHDL entity id.
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2009-02-16
Matthijs Kooijman
Put mkCompInsSm in the VHDLState monad.
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2009-02-13
Matthijs Kooijman
Make modFuncs work with stateful functions.
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2009-02-13
Matthijs Kooijman
Generate dummy component instantiations for each archit...
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2009-02-13
Matthijs Kooijman
Use less general names as labels some fields.
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2009-02-13
Matthijs Kooijman
Generate a VHDL architecture for each function.
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2009-02-13
Matthijs Kooijman
Add port declarations to the VHDL entities.
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2009-02-13
Matthijs Kooijman
Put a TypeMark in a VHDLSignalmap.
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2009-02-13
Matthijs Kooijman
Rename fields of SignalInfo.
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2009-02-13
Matthijs Kooijman
Extract entities from the session and return them in...
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2009-02-13
Matthijs Kooijman
Generate VHDL entity declarations.
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2009-02-13
Matthijs Kooijman
Create an entity for each function.
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2009-02-13
Matthijs Kooijman
Remove NamedFlatFunction again.
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2009-02-11
Matthijs Kooijman
Move around a bunch of types.
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2009-02-11
Matthijs Kooijman
Greatly clean up Translator.
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