Generate VHDL typecasts for literals when needed.
authorMatthijs Kooijman <m.kooijman@student.utwente.nl>
Tue, 14 Apr 2009 09:51:38 +0000 (11:51 +0200)
committerMatthijs Kooijman <m.kooijman@student.utwente.nl>
Tue, 14 Apr 2009 09:51:38 +0000 (11:51 +0200)
commit5e5a75ab40e00110d5169b6713a7786978d91c04
tree70b027d7dd8273cce75930dfc43c3a8d6327691b
parent91eeebebe020ba25922312f642765eaf82ac704a
Generate VHDL typecasts for literals when needed.
VHDL.hs