Translate the SizedWord type to a VHDL vector.
authorMatthijs Kooijman <m.kooijman@student.utwente.nl>
Thu, 9 Apr 2009 16:18:29 +0000 (18:18 +0200)
committerMatthijs Kooijman <m.kooijman@student.utwente.nl>
Thu, 9 Apr 2009 16:18:50 +0000 (18:18 +0200)
commita3ff46ea19a1966c2268fe99df24c15d04abc000
tree4b343f06995c9d7370098e2e21d1f83d1ffdd5ca
parent430a309686dbaf585844dc129cf7b6aa8568b652
Translate the SizedWord type to a VHDL vector.
VHDL.hs