Cabalized clash

diff --git a/.gitignore b/.gitignore
index 31ab9cc4dd2060a378a02f96f595520bdbd4287b..eefec2f56f199f24e1275d51aad1355bc81dd865 100644 (file)
--- a/.gitignore
+++ b/.gitignore
@@ -1,3 +1,4 @@
 *.hi
 *.o
 *.swp
+dist

diff --git a/Main.hs b/Main.hs
new file mode 100644 (file)
index 0000000..be0a0a0
--- /dev/null
+++ b/Main.hs
@@ -0,0 +1,6 @@
+module Main where
+
+import Translator
+
+main = do
+  makeVHDL "Alu.hs" "exec" True
\ No newline at end of file

diff --git a/Translator.hs b/Translator.hs
index 1ce9307d72992452d5bfe8415e667d3823c46c59..550b4f0800475b348d4a6146aa317527d74af79d 100644 (file)
--- a/Translator.hs
+++ b/Translator.hs
@@ -48,8 +48,8 @@ import FlattenTypes
 import VHDLTypes
 import qualified VHDL
 
-main = do
-  makeVHDL "Alu.hs" "exec" True
+-- main = do
+--   makeVHDL "Alu.hs" "exec" True
 
 makeVHDL :: String -> String -> Bool -> IO ()
 makeVHDL filename name stateful = do

diff --git a/VHDL.hs b/VHDL.hs
index b8fcab1d981e195946ab2485adc687f9ad2e4028..c5635046998c196f4ed4cded551dd0ddf827a002 100644 (file)
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -34,6 +34,9 @@ import TranslatorTypes
 import HsValueMap
 import Pretty
 import CoreTools
+import Constants
+import Generate
+import GlobalNameTable
 
 createDesignFiles ::
   FlatFuncMap

diff --git a/VHDLTypes.hs b/VHDLTypes.hs
index 33010822b9ace9ec74e0002e0ba015fd2643254b..a5d1569eb5728ebce6ec43223f5446674383bf9e 100644 (file)
--- a/VHDLTypes.hs
+++ b/VHDLTypes.hs
@@ -47,6 +47,9 @@ type TypeMap = Map.Map OrdType (AST.VHDLId, AST.TypeDec)
 -- A map of a Haskell function to a hardware signature
 type SignatureMap = Map.Map HsFunction Entity
 
+-- A map of a builtin function to VHDL function builder 
+type NameTable = Map.Map String (Int, [AST.Expr] -> AST.Expr )
+
 data VHDLSession = VHDLSession {
   -- | A map of Core type -> VHDL Type
   vsTypes_ :: TypeMap,

diff --git a/cλash.cabal b/cλash.cabal
new file mode 100644 (file)
index 0000000..798b281
--- /dev/null
+++ b/cλash.cabal
@@ -0,0 +1,21 @@
+name:                clash
+version:             0.1
+build-type:          Simple
+synopsis:            CAES Languege for Hardware Descriptions (CλasH)
+description:         CλasH is a toolchain/language to translate subsets of Haskell to synthesizable VHDL. It does this by translating the intermediate System Fc (GHC Core) representation to a VHDL AST, which is then written to file.
+category:            Development
+license:             BSD3
+license-file:        LICENSE
+package-url:         http://github.com/darchon/clash/tree/master
+copyright:           Copyright (c) 2009 Christiaan Baaij & Matthijs Kooijman
+author:              Christiaan Baaij & Matthijs Kooijman
+stability:           alpha
+maintainer:          christiaan.baaij@gmail.com & matthijs@stdin.nl
+build-depends:       base > 4, syb, ghc, ghc-paths, transformers, haskell98,
+                     ForSyDe, regex-posix ,data-accessor-template, pretty,
+                     data-accessor, containers, prettyclass, tfp > 0.3, 
+                     tfvec, QuickCheck, template-haskell
+
+executable:          clash
+main-is:             Main.hs     
+ghc-options: