matthijs/master-project/cλash.git
15 years agoMake register_bank work, with a bunch of changes.
Matthijs Kooijman [Thu, 19 Feb 2009 12:14:13 +0000 (13:14 +0100)]
Make register_bank work, with a bunch of changes.

Add special casing for the "fst", "snd", "patError" and "==" functions.

Add literal and equality tests to the SignalExpr type.

Allow data constructors to be used in expression, when they have a
corresponding literal in VHDL.

Allow full expressions to be scrutinized instead of just variables.

Perhaps more...

15 years agoLet zipValueMapsWith show the trees in the error.
Matthijs Kooijman [Thu, 19 Feb 2009 12:11:24 +0000 (13:11 +0100)]
Let zipValueMapsWith show the trees in the error.

15 years agoUse tuples instead of a ADT for the register bank state.
Matthijs Kooijman [Thu, 19 Feb 2009 12:10:10 +0000 (13:10 +0100)]
Use tuples instead of a ADT for the register bank state.

We can't translate ADT's yet, but tuples work.

15 years agoAdd space in error message.
Matthijs Kooijman [Thu, 19 Feb 2009 10:42:41 +0000 (11:42 +0100)]
Add space in error message.

15 years agoMake listBind also show a pretty printed output.
Matthijs Kooijman [Thu, 19 Feb 2009 10:36:46 +0000 (11:36 +0100)]
Make listBind also show a pretty printed output.

15 years agoFurther reduce main and add a makeVHDL function.
Matthijs Kooijman [Thu, 19 Feb 2009 10:35:13 +0000 (11:35 +0100)]
Further reduce main and add a makeVHDL function.

15 years agoSupport multiple alternative case expressions.
Matthijs Kooijman [Thu, 19 Feb 2009 10:26:25 +0000 (11:26 +0100)]
Support multiple alternative case expressions.

Currently, only Bit expressions can be scrutinized.

This also enhances the SigDefs to support expressions (only comparison
with a literal currently) in unconditional definitions.

15 years agoAdd stateful alu (with empty state).
Matthijs Kooijman [Thu, 19 Feb 2009 10:24:01 +0000 (11:24 +0100)]
Add stateful alu (with empty state).

15 years agoAdd a simple four-bit shift register model.
Matthijs Kooijman [Wed, 18 Feb 2009 19:27:20 +0000 (20:27 +0100)]
Add a simple four-bit shift register model.

This model is already translatable to VHDL.

15 years agoUse a different approach for marking SigUses.
Matthijs Kooijman [Wed, 18 Feb 2009 19:23:07 +0000 (20:23 +0100)]
Use a different approach for marking SigUses.

This approach iterates the use and signal maps once, instead of twice for
both ports and state.

This also ensures that a signal has at most a single use, a signal is
duplicated otherwise.

This commit makes the dff hardware model synthesize again.

15 years agoAdd setSignalInfo accessor for FlattenState.
Matthijs Kooijman [Wed, 18 Feb 2009 19:18:36 +0000 (20:18 +0100)]
Add setSignalInfo accessor for FlattenState.

15 years agoGenerate VHDL for UncondDefs.
Matthijs Kooijman [Wed, 18 Feb 2009 18:38:10 +0000 (19:38 +0100)]
Generate VHDL for UncondDefs.

15 years agoAdd a getSignalInfo accessor.
Matthijs Kooijman [Wed, 18 Feb 2009 18:30:20 +0000 (19:30 +0100)]
Add a getSignalInfo accessor.

15 years agoAdd a listBind function to show the Core for a bind.
Matthijs Kooijman [Wed, 18 Feb 2009 15:06:20 +0000 (16:06 +0100)]
Add a listBind function to show the Core for a bind.

This function is meant to be used from the ghci console.

15 years agoSplit out the large main function a bit.
Matthijs Kooijman [Wed, 18 Feb 2009 15:02:05 +0000 (16:02 +0100)]
Split out the large main function a bit.

This greatly reduces the amount of code running inside the Ghc monad.

15 years agoRemove the DontCare value from the Bit type.
Matthijs Kooijman [Wed, 18 Feb 2009 14:40:02 +0000 (15:40 +0100)]
Remove the DontCare value from the Bit type.

For now this will complicate the translator, so we'll see about DontCare
again when we're ready for it.

15 years agoDerive and use show instead of ppr to display Exprs.
Matthijs Kooijman [Wed, 18 Feb 2009 14:37:32 +0000 (15:37 +0100)]
Derive and use show instead of ppr to display Exprs.

This shows the actual data structures used in an expression more clearly,
without hiding details like ppr does.

15 years agoFix comment indent.
Matthijs Kooijman [Wed, 18 Feb 2009 14:36:25 +0000 (15:36 +0100)]
Fix comment indent.

15 years agoGeneralize FApp and CondDef into SigDef and add UncondDef.
Matthijs Kooijman [Tue, 17 Feb 2009 17:08:47 +0000 (18:08 +0100)]
Generalize FApp and CondDef into SigDef and add UncondDef.

15 years agoAdd a type alias StateId for state numbers.
Matthijs Kooijman [Tue, 17 Feb 2009 16:50:05 +0000 (17:50 +0100)]
Add a type alias StateId for state numbers.

15 years agoRemove type parameterisation of SignalMap.
Matthijs Kooijman [Tue, 17 Feb 2009 16:47:43 +0000 (17:47 +0100)]
Remove type parameterisation of SignalMap.

15 years agoDon't generate ports for non-port signals.
Matthijs Kooijman [Tue, 17 Feb 2009 16:36:27 +0000 (17:36 +0100)]
Don't generate ports for non-port signals.

This allows an entry in a VHDLSignalmap to be empty, which allows for
arguments and results that do not expand into a port, such as state.

15 years agoGenerate VHDL signals for internal signals and state.
Matthijs Kooijman [Tue, 17 Feb 2009 16:13:53 +0000 (17:13 +0100)]
Generate VHDL signals for internal signals and state.

15 years agoAdd predicates for SigUse.
Matthijs Kooijman [Tue, 17 Feb 2009 16:10:57 +0000 (17:10 +0100)]
Add predicates for SigUse.

15 years agoMark all signals as ports or states when appropriate.
Matthijs Kooijman [Tue, 17 Feb 2009 15:55:16 +0000 (16:55 +0100)]
Mark all signals as ports or states when appropriate.

Additionally, this differentiates between input and output ports and old
and new state.

15 years agoAlways import IEEE.std_logic_1164 in the generated VHDL.
Matthijs Kooijman [Tue, 17 Feb 2009 14:58:31 +0000 (15:58 +0100)]
Always import IEEE.std_logic_1164 in the generated VHDL.

15 years agoMove the DesignFile creation to VHDL.
Matthijs Kooijman [Tue, 17 Feb 2009 14:52:57 +0000 (15:52 +0100)]
Move the DesignFile creation to VHDL.

15 years agoAdd clk port on any stateful entity.
Matthijs Kooijman [Tue, 17 Feb 2009 14:49:24 +0000 (15:49 +0100)]
Add clk port on any stateful entity.

15 years agoCreate state procs for state signals.
Matthijs Kooijman [Tue, 17 Feb 2009 14:35:19 +0000 (15:35 +0100)]
Create state procs for state signals.

15 years agoMark port signals as such during flattening.
Matthijs Kooijman [Mon, 16 Feb 2009 16:22:20 +0000 (17:22 +0100)]
Mark port signals as such during flattening.

15 years agoImprove the pretty output of the signal list.
Matthijs Kooijman [Mon, 16 Feb 2009 16:11:13 +0000 (17:11 +0100)]
Improve the pretty output of the signal list.

15 years agoMake the pretty output more pretty.
Matthijs Kooijman [Mon, 16 Feb 2009 15:59:29 +0000 (16:59 +0100)]
Make the pretty output more pretty.

This prevents an unwanted wrap in the output.

15 years agoReduce genSignals to a single line using Traversable.
Matthijs Kooijman [Mon, 16 Feb 2009 15:58:38 +0000 (16:58 +0100)]
Reduce genSignals to a single line using Traversable.

15 years agoStore a use for each signal in a flattened function.
Matthijs Kooijman [Mon, 16 Feb 2009 15:50:35 +0000 (16:50 +0100)]
Store a use for each signal in a flattened function.

This allows us to differentiate between ports, signals and states more
easily (which is already possible but not so easy right now) and allows
us to differentiate between own state and substate later on.

Currently, all signals are marked as SigInternal.

15 years agoAdd port maps to component instantiations.
Matthijs Kooijman [Mon, 16 Feb 2009 12:35:32 +0000 (13:35 +0100)]
Add port maps to component instantiations.

15 years agoMake application names unique.
Matthijs Kooijman [Mon, 16 Feb 2009 12:05:18 +0000 (13:05 +0100)]
Make application names unique.

15 years agoAdd Entities for builtin functions.
Matthijs Kooijman [Mon, 16 Feb 2009 12:01:43 +0000 (13:01 +0100)]
Add Entities for builtin functions.

15 years agoLet mkCompInsSm look up the actual VHDL entity id.
Matthijs Kooijman [Mon, 16 Feb 2009 12:01:28 +0000 (13:01 +0100)]
Let mkCompInsSm look up the actual VHDL entity id.

Previously, it would always instantiate "foo". This also adds another
entity id field to the "Entity" type, since builtin function don't have a
VHDL EntityDec, but do need an id.

15 years agoPut mkCompInsSm in the VHDLState monad.
Matthijs Kooijman [Mon, 16 Feb 2009 11:27:10 +0000 (12:27 +0100)]
Put mkCompInsSm in the VHDLState monad.

15 years agoMake modFuncs work with stateful functions.
Matthijs Kooijman [Fri, 13 Feb 2009 15:04:32 +0000 (16:04 +0100)]
Make modFuncs work with stateful functions.

This allows createArchitecture and createEntity to access the current
session.

15 years agoGeneralize some session modification functions.
Matthijs Kooijman [Fri, 13 Feb 2009 14:49:49 +0000 (15:49 +0100)]
Generalize some session modification functions.

15 years agoGenerate dummy component instantiations for each architecture.
Matthijs Kooijman [Fri, 13 Feb 2009 14:12:21 +0000 (15:12 +0100)]
Generate dummy component instantiations for each architecture.

We don't have a session available, so we can't lookup or generate any
names yet. Also, the portmaps are not implemented yet.

15 years agoMove some pretty printing code around.
Matthijs Kooijman [Fri, 13 Feb 2009 13:54:00 +0000 (14:54 +0100)]
Move some pretty printing code around.

15 years agoUse less general names as labels some fields.
Matthijs Kooijman [Fri, 13 Feb 2009 13:49:30 +0000 (14:49 +0100)]
Use less general names as labels some fields.

15 years agoGenerate a VHDL architecture for each function.
Matthijs Kooijman [Fri, 13 Feb 2009 13:45:05 +0000 (14:45 +0100)]
Generate a VHDL architecture for each function.

The architecture contains signal declarations, but no instantiations yet.

15 years agoAdd port declarations to the VHDL entities.
Matthijs Kooijman [Fri, 13 Feb 2009 13:07:06 +0000 (14:07 +0100)]
Add port declarations to the VHDL entities.

15 years agoPut a TypeMark in a VHDLSignalmap.
Matthijs Kooijman [Fri, 13 Feb 2009 12:43:51 +0000 (13:43 +0100)]
Put a TypeMark in a VHDLSignalmap.

15 years agoRename fields of SignalInfo.
Matthijs Kooijman [Fri, 13 Feb 2009 12:38:08 +0000 (13:38 +0100)]
Rename fields of SignalInfo.

15 years agoStore the Haskell Type in SignalInfo.
Matthijs Kooijman [Fri, 13 Feb 2009 12:36:20 +0000 (13:36 +0100)]
Store the Haskell Type in SignalInfo.

15 years agoAdd the VHDLTypes module
Matthijs Kooijman [Fri, 13 Feb 2009 11:39:29 +0000 (12:39 +0100)]
Add the VHDLTypes module

This file should have been added a few commits back already...

15 years agoExtract entities from the session and return them in the design file.
Matthijs Kooijman [Fri, 13 Feb 2009 11:37:19 +0000 (12:37 +0100)]
Extract entities from the session and return them in the design file.

15 years agoGenerate VHDL entity declarations.
Matthijs Kooijman [Fri, 13 Feb 2009 11:28:36 +0000 (12:28 +0100)]
Generate VHDL entity declarations.

These declarations are still without ports and with a name that might not
be unique, though.

15 years agoCreate an entity for each function.
Matthijs Kooijman [Fri, 13 Feb 2009 11:17:58 +0000 (12:17 +0100)]
Create an entity for each function.

The entity does not yet contain the actual VHDL entity, but does contain
the argument / result to port name map.

15 years agoStore signals in a map.
Matthijs Kooijman [Fri, 13 Feb 2009 10:11:33 +0000 (11:11 +0100)]
Store signals in a map.

This turns the list of Signals into a list of (sigid, SignalInfo), which
enables lookup by id.

15 years agoName signals in a function after flattening it.
Matthijs Kooijman [Fri, 13 Feb 2009 09:43:09 +0000 (10:43 +0100)]
Name signals in a function after flattening it.

15 years agoAdd a modFunc function to edit a function in the session.
Matthijs Kooijman [Fri, 13 Feb 2009 08:55:53 +0000 (09:55 +0100)]
Add a modFunc function to edit a function in the session.

15 years agoRemove NamedFlatFunction again.
Matthijs Kooijman [Fri, 13 Feb 2009 08:55:29 +0000 (09:55 +0100)]
Remove NamedFlatFunction again.

We'll use another way to represent names in FlatFunctions.

15 years agoAllow a FlatFunction to be named as well as unnamed.
Matthijs Kooijman [Wed, 11 Feb 2009 19:22:07 +0000 (20:22 +0100)]
Allow a FlatFunction to be named as well as unnamed.

15 years agoFill the signal list in FlatFunction.
Matthijs Kooijman [Wed, 11 Feb 2009 19:13:10 +0000 (20:13 +0100)]
Fill the signal list in FlatFunction.

15 years agoAdd a list of used signals to FlatFunction.
Matthijs Kooijman [Wed, 11 Feb 2009 19:07:46 +0000 (20:07 +0100)]
Add a list of used signals to FlatFunction.

15 years agoRemove the distinction between SignalDef and SignalUse.
Matthijs Kooijman [Wed, 11 Feb 2009 19:01:44 +0000 (20:01 +0100)]
Remove the distinction between SignalDef and SignalUse.

Now everywhere SignalDef and SignalUse was used before, the sigid is used
directly.

15 years agoMake FlatFunction parameterized with the signal id type.
Matthijs Kooijman [Wed, 11 Feb 2009 18:53:47 +0000 (19:53 +0100)]
Make FlatFunction parameterized with the signal id type.

This allows us to define a NamedFlatFunction later on where the signals
have names.

15 years agoMove around a bunch of types.
Matthijs Kooijman [Wed, 11 Feb 2009 18:38:57 +0000 (19:38 +0100)]
Move around a bunch of types.

Now most types are defined in a separate module, making it easier to
prevent circular dependencies.

15 years agoAdd more builtin functions.
Matthijs Kooijman [Wed, 11 Feb 2009 17:58:53 +0000 (18:58 +0100)]
Add more builtin functions.

15 years agoOnly force a stateful interface for top level functions.
Matthijs Kooijman [Wed, 11 Feb 2009 17:58:02 +0000 (18:58 +0100)]
Only force a stateful interface for top level functions.

15 years agoAdd facilities for builtin functions.
Matthijs Kooijman [Wed, 11 Feb 2009 17:44:58 +0000 (18:44 +0100)]
Add facilities for builtin functions.

15 years agoAdd a setFlatFunc function.
Matthijs Kooijman [Wed, 11 Feb 2009 17:39:50 +0000 (18:39 +0100)]
Add a setFlatFunc function.

This function allows for associating a FlatFunction with a HsFunction in
the current session.

15 years agoMake the flatfunc in FuncMap optional.
Matthijs Kooijman [Wed, 11 Feb 2009 17:32:41 +0000 (18:32 +0100)]
Make the flatfunc in FuncMap optional.

15 years agoReplace FuncMap by a Data.Map.
Matthijs Kooijman [Wed, 11 Feb 2009 17:31:34 +0000 (18:31 +0100)]
Replace FuncMap by a Data.Map.

15 years agoDerive Ord for HsFunction.
Matthijs Kooijman [Wed, 11 Feb 2009 17:23:05 +0000 (18:23 +0100)]
Derive Ord for HsFunction.

15 years agoImplement resolvFunc.
Matthijs Kooijman [Wed, 11 Feb 2009 17:07:51 +0000 (18:07 +0100)]
Implement resolvFunc.

This function looks for any used functions in the current module.

15 years agoAdd getFunc session accessor.
Matthijs Kooijman [Wed, 11 Feb 2009 17:06:56 +0000 (18:06 +0100)]
Add getFunc session accessor.

15 years agoAdd the current CoreModule to the session.
Matthijs Kooijman [Wed, 11 Feb 2009 16:56:13 +0000 (17:56 +0100)]
Add the current CoreModule to the session.

15 years agoReplace printBind* by a Pretty instance.
Matthijs Kooijman [Wed, 11 Feb 2009 16:47:12 +0000 (17:47 +0100)]
Replace printBind* by a Pretty instance.

15 years agoAdd Pretty instance for VHDLSession.
Matthijs Kooijman [Wed, 11 Feb 2009 16:28:05 +0000 (17:28 +0100)]
Add Pretty instance for VHDLSession.

15 years agoGreatly clean up Translator.
Matthijs Kooijman [Wed, 11 Feb 2009 16:27:09 +0000 (17:27 +0100)]
Greatly clean up Translator.

Translator now uses Flatten to flatten a function, but does not do
anything after that point yet. Some code is moved from Translator to the
new modules VHDL and TranslatorTypes, but a lot of other code is removed
(since it was duplicated in Flatten, or will be redone in VHDL).

15 years agoGive stateless a type signature.
Matthijs Kooijman [Wed, 11 Feb 2009 16:24:18 +0000 (17:24 +0100)]
Give stateless a type signature.

This ensures that any function that stateless is inlined into doesn't
become polymorph.

15 years agoAdd pretty printing functions for FlatFunction.
Matthijs Kooijman [Wed, 11 Feb 2009 14:39:57 +0000 (15:39 +0100)]
Add pretty printing functions for FlatFunction.

These pretty printing functions are based on Text.PrettyPrint.HughesPJ and
the related Text.PrettyPrint.HughesPJClass from the prettyclass package.

15 years agoLearn flattenExpr about single alt Case expressions.
Matthijs Kooijman [Wed, 11 Feb 2009 11:58:28 +0000 (12:58 +0100)]
Learn flattenExpr about single alt Case expressions.

15 years agoLearn flattenExpr about Let expressions.
Matthijs Kooijman [Wed, 11 Feb 2009 11:48:36 +0000 (12:48 +0100)]
Learn flattenExpr about Let expressions.

15 years agoLearn flattenExpr about building tuples.
Matthijs Kooijman [Wed, 11 Feb 2009 11:37:50 +0000 (12:37 +0100)]
Learn flattenExpr about building tuples.

15 years agoLearn flattenExpr to flatten normal applications.
Matthijs Kooijman [Wed, 11 Feb 2009 11:25:59 +0000 (12:25 +0100)]
Learn flattenExpr to flatten normal applications.

15 years agoAdd useAsPort and useAsState functions.
Matthijs Kooijman [Wed, 11 Feb 2009 11:05:59 +0000 (12:05 +0100)]
Add useAsPort and useAsState functions.

For this, HsValueMap is made Traversable and a PassState type to wrap a
function was added as well.

15 years agoAdd defMapTouseMap function.
Matthijs Kooijman [Mon, 9 Feb 2009 16:18:49 +0000 (17:18 +0100)]
Add defMapTouseMap function.

15 years agoMake HsValueMap an instance of Functor.
Matthijs Kooijman [Mon, 9 Feb 2009 16:18:40 +0000 (17:18 +0100)]
Make HsValueMap an instance of Functor.

15 years agoLearn flattenExpr about function application.
Matthijs Kooijman [Mon, 9 Feb 2009 15:20:26 +0000 (16:20 +0100)]
Learn flattenExpr about function application.

This only distinguishes tuple construction, other data constructor
application and other function applications, but does not actually flatten
any of these yet.

15 years agoMake flattenExpr return signal definitions for arguments.
Matthijs Kooijman [Mon, 9 Feb 2009 15:00:01 +0000 (16:00 +0100)]
Make flattenExpr return signal definitions for arguments.

This makes the "wire" example be flattened properly.

15 years agoLearn flattenExpr about Var expressions.
Matthijs Kooijman [Mon, 9 Feb 2009 14:53:10 +0000 (15:53 +0100)]
Learn flattenExpr about Var expressions.

15 years agoLearn flattenExpr about Lambda expressions.
Matthijs Kooijman [Mon, 9 Feb 2009 14:36:03 +0000 (15:36 +0100)]
Learn flattenExpr about Lambda expressions.

15 years agoAdd a BindMap argument to flattenExpr.
Matthijs Kooijman [Fri, 6 Feb 2009 11:23:25 +0000 (12:23 +0100)]
Add a BindMap argument to flattenExpr.

15 years agoAdd accessor methods for FlattenState.
Matthijs Kooijman [Fri, 6 Feb 2009 11:19:36 +0000 (12:19 +0100)]
Add accessor methods for FlattenState.

15 years agoAdd flattenFunction and flattenExpr.
Matthijs Kooijman [Fri, 6 Feb 2009 11:13:13 +0000 (12:13 +0100)]
Add flattenFunction and flattenExpr.

This does not add any actual implementation for flattenExpr, just an empty
function.

This also duplicates the HsValueMap type from Translator, to prevent
dependency loops when testing.

15 years agoAdd a new module "Flatten".
Matthijs Kooijman [Fri, 6 Feb 2009 08:36:59 +0000 (09:36 +0100)]
Add a new module "Flatten".

Only contains data structures so far, but this module will also contain
code for translaten Core to FlatFunctions.

15 years agoLet Translator.hs export everything.
Matthijs Kooijman [Fri, 6 Feb 2009 08:36:31 +0000 (09:36 +0100)]
Let Translator.hs export everything.

15 years agoName the module in Translator.hs Translator.
Matthijs Kooijman [Thu, 5 Feb 2009 18:47:57 +0000 (19:47 +0100)]
Name the module in Translator.hs Translator.

The module was previously called Main.

15 years agoRemove the export list from the Alu module.
Matthijs Kooijman [Thu, 5 Feb 2009 08:20:34 +0000 (09:20 +0100)]
Remove the export list from the Alu module.

This means to export all functions in the module. Previously, it seems
that the alu function was inlined everywhere and thus dropped from the
function list.

15 years agoMake the arguments of the alu function curried.
Matthijs Kooijman [Thu, 5 Feb 2009 08:20:14 +0000 (09:20 +0100)]
Make the arguments of the alu function curried.

15 years agoRemove the empty state of the alu function.
Matthijs Kooijman [Thu, 5 Feb 2009 08:18:08 +0000 (09:18 +0100)]
Remove the empty state of the alu function.

15 years agoCreate a VHDL proc for each state variable.
Matthijs Kooijman [Tue, 3 Feb 2009 15:02:48 +0000 (16:02 +0100)]
Create a VHDL proc for each state variable.

This also requires that every entity has a clk inport. This should be
limited to stateful entities only later on.

15 years agoGenerate a list of state, signal pairs as a side effect of generating signal assignments.
Matthijs Kooijman [Tue, 3 Feb 2009 13:57:04 +0000 (14:57 +0100)]
Generate a list of state, signal pairs as a side effect of generating signal assignments.