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(parent: 21845a9) | patch
Create a VHDL proc for each state variable.
authorMatthijs Kooijman <m.kooijman@student.utwente.nl>
Tue, 3 Feb 2009 15:02:48 +0000 (16:02 +0100)
committerMatthijs Kooijman <m.kooijman@student.utwente.nl>
Tue, 3 Feb 2009 15:02:48 +0000 (16:02 +0100)
commitc69f7a9af50cc833d5cb3f66b61729d63b57d285
tree58afb3c68723bf6ca87c72c989eb23d10f3a1532tree | snapshot
parent21845a99566a16f1c727a845035c56d41978b337commit | diff
Create a VHDL proc for each state variable.

This also requires that every entity has a clk inport. This should be
limited to stateful entities only later on.
Translator.hs diff | blob | history
The Cλash compiler