matthijs/master-project/cλash.git
15 years agoMake createEntity preserve the Entity on builtin functions.
Matthijs Kooijman [Mon, 9 Mar 2009 09:26:42 +0000 (10:26 +0100)]
Make createEntity preserve the Entity on builtin functions.

15 years agoAdd a getFuncMap accessor for VHDLState.
Matthijs Kooijman [Fri, 6 Mar 2009 10:23:00 +0000 (11:23 +0100)]
Add a getFuncMap accessor for VHDLState.

15 years agoDerive Show for a bunch of types.
Matthijs Kooijman [Fri, 6 Mar 2009 10:22:47 +0000 (11:22 +0100)]
Derive Show for a bunch of types.

15 years agoMove the Show deriving for Core types to a new CoreShow module.
Matthijs Kooijman [Fri, 6 Mar 2009 10:21:55 +0000 (11:21 +0100)]
Move the Show deriving for Core types to a new CoreShow module.

15 years agoRemove the dontcare function from Bits.
Matthijs Kooijman [Thu, 5 Mar 2009 13:43:24 +0000 (14:43 +0100)]
Remove the dontcare function from Bits.

15 years agoRemove createEntity from the VHDLState monad.
Matthijs Kooijman [Thu, 5 Mar 2009 13:36:36 +0000 (14:36 +0100)]
Remove createEntity from the VHDLState monad.

15 years agoRemove getDesignFiles from the VHDLState monad.
Matthijs Kooijman [Thu, 5 Mar 2009 12:09:01 +0000 (13:09 +0100)]
Remove getDesignFiles from the VHDLState monad.

This also does some related cleanup.

15 years agoStrip adjacent underscores from VHDLIds.
Matthijs Kooijman [Thu, 5 Mar 2009 11:59:34 +0000 (12:59 +0100)]
Strip adjacent underscores from VHDLIds.

15 years agoProvide preliminary support for list types.
Matthijs Kooijman [Wed, 4 Mar 2009 21:11:36 +0000 (22:11 +0100)]
Provide preliminary support for list types.

Lot's of TODO's are left...

15 years agoAdd some hardware models using vectors (FSVec).
Matthijs Kooijman [Wed, 4 Mar 2009 21:10:58 +0000 (22:10 +0100)]
Add some hardware models using vectors (FSVec).

15 years agoFix propagateState removing all non-FApp SigDefs.
Matthijs Kooijman [Wed, 4 Mar 2009 10:35:42 +0000 (11:35 +0100)]
Fix propagateState removing all non-FApp SigDefs.

15 years agoMap the clk port on stateful function applications.
Matthijs Kooijman [Wed, 4 Mar 2009 10:35:08 +0000 (11:35 +0100)]
Map the clk port on stateful function applications.

15 years agoDon't inline alu.
Matthijs Kooijman [Wed, 4 Mar 2009 10:34:25 +0000 (11:34 +0100)]
Don't inline alu.

15 years agoRemove support for DontCare.
Matthijs Kooijman [Tue, 3 Mar 2009 23:54:09 +0000 (00:54 +0100)]
Remove support for DontCare.

15 years agoFill in propagateState.
Matthijs Kooijman [Tue, 3 Mar 2009 23:50:27 +0000 (00:50 +0100)]
Fill in propagateState.

15 years agoRemove the now obsolete getOwnStates.
Matthijs Kooijman [Tue, 3 Mar 2009 23:50:09 +0000 (00:50 +0100)]
Remove the now obsolete getOwnStates.

15 years agoAdd some predicates and accessors to FlattenTypes.
Matthijs Kooijman [Tue, 3 Mar 2009 23:49:43 +0000 (00:49 +0100)]
Add some predicates and accessors to FlattenTypes.

15 years agoLet VHDL use SignalInfo instead of HsFunction for generating states.
Matthijs Kooijman [Tue, 3 Mar 2009 23:34:40 +0000 (00:34 +0100)]
Let VHDL use SignalInfo instead of HsFunction for generating states.

This makes sure that any signals that will be marked SigSubState
won't get an extra state variable.

15 years agoAdd initial (dummy) propagateState function.
Matthijs Kooijman [Tue, 3 Mar 2009 11:24:57 +0000 (12:24 +0100)]
Add initial (dummy) propagateState function.

The propagateState function will propagate the state variables down to
called functions whenever possible. For now, it just leaves functions
unchanged.

15 years agoAdd vim modeline.
Matthijs Kooijman [Tue, 3 Mar 2009 11:21:57 +0000 (12:21 +0100)]
Add vim modeline.

15 years agoAdd a is_FApp predicate.
Matthijs Kooijman [Tue, 3 Mar 2009 11:21:35 +0000 (12:21 +0100)]
Add a is_FApp predicate.

15 years agoNever inline the half_adder function.
Matthijs Kooijman [Tue, 3 Mar 2009 10:58:25 +0000 (11:58 +0100)]
Never inline the half_adder function.

15 years agoAdd StandalonDeriving language option to Pretty.
Matthijs Kooijman [Tue, 3 Mar 2009 10:56:34 +0000 (11:56 +0100)]
Add StandalonDeriving language option to Pretty.

15 years agoDon't add duplicate name hints.
Matthijs Kooijman [Tue, 3 Mar 2009 10:56:05 +0000 (11:56 +0100)]
Don't add duplicate name hints.

15 years agoPut VHDL files for each design in a separate directory.
Matthijs Kooijman [Tue, 3 Mar 2009 09:22:04 +0000 (10:22 +0100)]
Put VHDL files for each design in a separate directory.

15 years agoAllow for generating VHDL for stateless functions.
Matthijs Kooijman [Tue, 3 Mar 2009 08:59:45 +0000 (09:59 +0100)]
Allow for generating VHDL for stateless functions.

Previously, the top level function needed to be stateful always. Now, the
makeVHDL function has a Bool argument to specify statefulness.

15 years agoAdd some newlines in the output.
Matthijs Kooijman [Fri, 27 Feb 2009 15:24:57 +0000 (16:24 +0100)]
Add some newlines in the output.

15 years agoMake exec have a single binding.
Matthijs Kooijman [Fri, 27 Feb 2009 13:37:55 +0000 (14:37 +0100)]
Make exec have a single binding.

This prevents two separate invocations of register_bank, which leads to
having a separate register bank for reading and writing.

15 years agoAdd a two-port mux hardware model.
Matthijs Kooijman [Fri, 27 Feb 2009 13:35:05 +0000 (14:35 +0100)]
Add a two-port mux hardware model.

15 years agoWrite each VHDL entity to a seperate file.
Matthijs Kooijman [Thu, 19 Feb 2009 15:15:16 +0000 (16:15 +0100)]
Write each VHDL entity to a seperate file.

15 years agoLet the exec function output something.
Matthijs Kooijman [Thu, 19 Feb 2009 15:14:52 +0000 (16:14 +0100)]
Let the exec function output something.

15 years agoSupport construction of empty tuples.
Matthijs Kooijman [Thu, 19 Feb 2009 14:48:58 +0000 (15:48 +0100)]
Support construction of empty tuples.

15 years agoPrint the list of signals sorted by id.
Matthijs Kooijman [Thu, 19 Feb 2009 14:31:14 +0000 (15:31 +0100)]
Print the list of signals sorted by id.

15 years agoAlso allow uppercase letters and a period in VHDL ids.
Matthijs Kooijman [Thu, 19 Feb 2009 14:13:45 +0000 (15:13 +0100)]
Also allow uppercase letters and a period in VHDL ids.

15 years agoAdd name hints to various signals generated.
Matthijs Kooijman [Thu, 19 Feb 2009 14:08:50 +0000 (15:08 +0100)]
Add name hints to various signals generated.

15 years agoStrip invalid characters from VHDL identifiers.
Matthijs Kooijman [Thu, 19 Feb 2009 14:06:02 +0000 (15:06 +0100)]
Strip invalid characters from VHDL identifiers.

15 years agoUse the name hints in signal name construction.
Matthijs Kooijman [Thu, 19 Feb 2009 13:29:36 +0000 (14:29 +0100)]
Use the name hints in signal name construction.

15 years agoDo the naming of a signal in named function instead of a lambda.
Matthijs Kooijman [Thu, 19 Feb 2009 13:26:13 +0000 (14:26 +0100)]
Do the naming of a signal in named function instead of a lambda.

15 years agoAllow name hints to be set for a signal.
Matthijs Kooijman [Thu, 19 Feb 2009 13:21:52 +0000 (14:21 +0100)]
Allow name hints to be set for a signal.

15 years agoEnable the DontCare value for Bit again.
Matthijs Kooijman [Thu, 19 Feb 2009 13:17:58 +0000 (14:17 +0100)]
Enable the DontCare value for Bit again.

This is still not completely fool-proof, improvements will follow.

15 years agoPrint the Defs list sorted.
Matthijs Kooijman [Thu, 19 Feb 2009 13:17:09 +0000 (14:17 +0100)]
Print the Defs list sorted.

15 years agoMake register_bank work, with a bunch of changes.
Matthijs Kooijman [Thu, 19 Feb 2009 12:14:13 +0000 (13:14 +0100)]
Make register_bank work, with a bunch of changes.

Add special casing for the "fst", "snd", "patError" and "==" functions.

Add literal and equality tests to the SignalExpr type.

Allow data constructors to be used in expression, when they have a
corresponding literal in VHDL.

Allow full expressions to be scrutinized instead of just variables.

Perhaps more...

15 years agoLet zipValueMapsWith show the trees in the error.
Matthijs Kooijman [Thu, 19 Feb 2009 12:11:24 +0000 (13:11 +0100)]
Let zipValueMapsWith show the trees in the error.

15 years agoUse tuples instead of a ADT for the register bank state.
Matthijs Kooijman [Thu, 19 Feb 2009 12:10:10 +0000 (13:10 +0100)]
Use tuples instead of a ADT for the register bank state.

We can't translate ADT's yet, but tuples work.

15 years agoAdd space in error message.
Matthijs Kooijman [Thu, 19 Feb 2009 10:42:41 +0000 (11:42 +0100)]
Add space in error message.

15 years agoMake listBind also show a pretty printed output.
Matthijs Kooijman [Thu, 19 Feb 2009 10:36:46 +0000 (11:36 +0100)]
Make listBind also show a pretty printed output.

15 years agoFurther reduce main and add a makeVHDL function.
Matthijs Kooijman [Thu, 19 Feb 2009 10:35:13 +0000 (11:35 +0100)]
Further reduce main and add a makeVHDL function.

15 years agoSupport multiple alternative case expressions.
Matthijs Kooijman [Thu, 19 Feb 2009 10:26:25 +0000 (11:26 +0100)]
Support multiple alternative case expressions.

Currently, only Bit expressions can be scrutinized.

This also enhances the SigDefs to support expressions (only comparison
with a literal currently) in unconditional definitions.

15 years agoAdd stateful alu (with empty state).
Matthijs Kooijman [Thu, 19 Feb 2009 10:24:01 +0000 (11:24 +0100)]
Add stateful alu (with empty state).

15 years agoAdd a simple four-bit shift register model.
Matthijs Kooijman [Wed, 18 Feb 2009 19:27:20 +0000 (20:27 +0100)]
Add a simple four-bit shift register model.

This model is already translatable to VHDL.

15 years agoUse a different approach for marking SigUses.
Matthijs Kooijman [Wed, 18 Feb 2009 19:23:07 +0000 (20:23 +0100)]
Use a different approach for marking SigUses.

This approach iterates the use and signal maps once, instead of twice for
both ports and state.

This also ensures that a signal has at most a single use, a signal is
duplicated otherwise.

This commit makes the dff hardware model synthesize again.

15 years agoAdd setSignalInfo accessor for FlattenState.
Matthijs Kooijman [Wed, 18 Feb 2009 19:18:36 +0000 (20:18 +0100)]
Add setSignalInfo accessor for FlattenState.

15 years agoGenerate VHDL for UncondDefs.
Matthijs Kooijman [Wed, 18 Feb 2009 18:38:10 +0000 (19:38 +0100)]
Generate VHDL for UncondDefs.

15 years agoAdd a getSignalInfo accessor.
Matthijs Kooijman [Wed, 18 Feb 2009 18:30:20 +0000 (19:30 +0100)]
Add a getSignalInfo accessor.

15 years agoAdd a listBind function to show the Core for a bind.
Matthijs Kooijman [Wed, 18 Feb 2009 15:06:20 +0000 (16:06 +0100)]
Add a listBind function to show the Core for a bind.

This function is meant to be used from the ghci console.

15 years agoSplit out the large main function a bit.
Matthijs Kooijman [Wed, 18 Feb 2009 15:02:05 +0000 (16:02 +0100)]
Split out the large main function a bit.

This greatly reduces the amount of code running inside the Ghc monad.

15 years agoRemove the DontCare value from the Bit type.
Matthijs Kooijman [Wed, 18 Feb 2009 14:40:02 +0000 (15:40 +0100)]
Remove the DontCare value from the Bit type.

For now this will complicate the translator, so we'll see about DontCare
again when we're ready for it.

15 years agoDerive and use show instead of ppr to display Exprs.
Matthijs Kooijman [Wed, 18 Feb 2009 14:37:32 +0000 (15:37 +0100)]
Derive and use show instead of ppr to display Exprs.

This shows the actual data structures used in an expression more clearly,
without hiding details like ppr does.

15 years agoFix comment indent.
Matthijs Kooijman [Wed, 18 Feb 2009 14:36:25 +0000 (15:36 +0100)]
Fix comment indent.

15 years agoGeneralize FApp and CondDef into SigDef and add UncondDef.
Matthijs Kooijman [Tue, 17 Feb 2009 17:08:47 +0000 (18:08 +0100)]
Generalize FApp and CondDef into SigDef and add UncondDef.

15 years agoAdd a type alias StateId for state numbers.
Matthijs Kooijman [Tue, 17 Feb 2009 16:50:05 +0000 (17:50 +0100)]
Add a type alias StateId for state numbers.

15 years agoRemove type parameterisation of SignalMap.
Matthijs Kooijman [Tue, 17 Feb 2009 16:47:43 +0000 (17:47 +0100)]
Remove type parameterisation of SignalMap.

15 years agoDon't generate ports for non-port signals.
Matthijs Kooijman [Tue, 17 Feb 2009 16:36:27 +0000 (17:36 +0100)]
Don't generate ports for non-port signals.

This allows an entry in a VHDLSignalmap to be empty, which allows for
arguments and results that do not expand into a port, such as state.

15 years agoGenerate VHDL signals for internal signals and state.
Matthijs Kooijman [Tue, 17 Feb 2009 16:13:53 +0000 (17:13 +0100)]
Generate VHDL signals for internal signals and state.

15 years agoAdd predicates for SigUse.
Matthijs Kooijman [Tue, 17 Feb 2009 16:10:57 +0000 (17:10 +0100)]
Add predicates for SigUse.

15 years agoMark all signals as ports or states when appropriate.
Matthijs Kooijman [Tue, 17 Feb 2009 15:55:16 +0000 (16:55 +0100)]
Mark all signals as ports or states when appropriate.

Additionally, this differentiates between input and output ports and old
and new state.

15 years agoAlways import IEEE.std_logic_1164 in the generated VHDL.
Matthijs Kooijman [Tue, 17 Feb 2009 14:58:31 +0000 (15:58 +0100)]
Always import IEEE.std_logic_1164 in the generated VHDL.

15 years agoMove the DesignFile creation to VHDL.
Matthijs Kooijman [Tue, 17 Feb 2009 14:52:57 +0000 (15:52 +0100)]
Move the DesignFile creation to VHDL.

15 years agoAdd clk port on any stateful entity.
Matthijs Kooijman [Tue, 17 Feb 2009 14:49:24 +0000 (15:49 +0100)]
Add clk port on any stateful entity.

15 years agoCreate state procs for state signals.
Matthijs Kooijman [Tue, 17 Feb 2009 14:35:19 +0000 (15:35 +0100)]
Create state procs for state signals.

15 years agoMark port signals as such during flattening.
Matthijs Kooijman [Mon, 16 Feb 2009 16:22:20 +0000 (17:22 +0100)]
Mark port signals as such during flattening.

15 years agoImprove the pretty output of the signal list.
Matthijs Kooijman [Mon, 16 Feb 2009 16:11:13 +0000 (17:11 +0100)]
Improve the pretty output of the signal list.

15 years agoMake the pretty output more pretty.
Matthijs Kooijman [Mon, 16 Feb 2009 15:59:29 +0000 (16:59 +0100)]
Make the pretty output more pretty.

This prevents an unwanted wrap in the output.

15 years agoReduce genSignals to a single line using Traversable.
Matthijs Kooijman [Mon, 16 Feb 2009 15:58:38 +0000 (16:58 +0100)]
Reduce genSignals to a single line using Traversable.

15 years agoStore a use for each signal in a flattened function.
Matthijs Kooijman [Mon, 16 Feb 2009 15:50:35 +0000 (16:50 +0100)]
Store a use for each signal in a flattened function.

This allows us to differentiate between ports, signals and states more
easily (which is already possible but not so easy right now) and allows
us to differentiate between own state and substate later on.

Currently, all signals are marked as SigInternal.

15 years agoAdd port maps to component instantiations.
Matthijs Kooijman [Mon, 16 Feb 2009 12:35:32 +0000 (13:35 +0100)]
Add port maps to component instantiations.

15 years agoMake application names unique.
Matthijs Kooijman [Mon, 16 Feb 2009 12:05:18 +0000 (13:05 +0100)]
Make application names unique.

15 years agoAdd Entities for builtin functions.
Matthijs Kooijman [Mon, 16 Feb 2009 12:01:43 +0000 (13:01 +0100)]
Add Entities for builtin functions.

15 years agoLet mkCompInsSm look up the actual VHDL entity id.
Matthijs Kooijman [Mon, 16 Feb 2009 12:01:28 +0000 (13:01 +0100)]
Let mkCompInsSm look up the actual VHDL entity id.

Previously, it would always instantiate "foo". This also adds another
entity id field to the "Entity" type, since builtin function don't have a
VHDL EntityDec, but do need an id.

15 years agoPut mkCompInsSm in the VHDLState monad.
Matthijs Kooijman [Mon, 16 Feb 2009 11:27:10 +0000 (12:27 +0100)]
Put mkCompInsSm in the VHDLState monad.

15 years agoMake modFuncs work with stateful functions.
Matthijs Kooijman [Fri, 13 Feb 2009 15:04:32 +0000 (16:04 +0100)]
Make modFuncs work with stateful functions.

This allows createArchitecture and createEntity to access the current
session.

15 years agoGeneralize some session modification functions.
Matthijs Kooijman [Fri, 13 Feb 2009 14:49:49 +0000 (15:49 +0100)]
Generalize some session modification functions.

15 years agoGenerate dummy component instantiations for each architecture.
Matthijs Kooijman [Fri, 13 Feb 2009 14:12:21 +0000 (15:12 +0100)]
Generate dummy component instantiations for each architecture.

We don't have a session available, so we can't lookup or generate any
names yet. Also, the portmaps are not implemented yet.

15 years agoMove some pretty printing code around.
Matthijs Kooijman [Fri, 13 Feb 2009 13:54:00 +0000 (14:54 +0100)]
Move some pretty printing code around.

15 years agoUse less general names as labels some fields.
Matthijs Kooijman [Fri, 13 Feb 2009 13:49:30 +0000 (14:49 +0100)]
Use less general names as labels some fields.

15 years agoGenerate a VHDL architecture for each function.
Matthijs Kooijman [Fri, 13 Feb 2009 13:45:05 +0000 (14:45 +0100)]
Generate a VHDL architecture for each function.

The architecture contains signal declarations, but no instantiations yet.

15 years agoAdd port declarations to the VHDL entities.
Matthijs Kooijman [Fri, 13 Feb 2009 13:07:06 +0000 (14:07 +0100)]
Add port declarations to the VHDL entities.

15 years agoPut a TypeMark in a VHDLSignalmap.
Matthijs Kooijman [Fri, 13 Feb 2009 12:43:51 +0000 (13:43 +0100)]
Put a TypeMark in a VHDLSignalmap.

15 years agoRename fields of SignalInfo.
Matthijs Kooijman [Fri, 13 Feb 2009 12:38:08 +0000 (13:38 +0100)]
Rename fields of SignalInfo.

15 years agoStore the Haskell Type in SignalInfo.
Matthijs Kooijman [Fri, 13 Feb 2009 12:36:20 +0000 (13:36 +0100)]
Store the Haskell Type in SignalInfo.

15 years agoAdd the VHDLTypes module
Matthijs Kooijman [Fri, 13 Feb 2009 11:39:29 +0000 (12:39 +0100)]
Add the VHDLTypes module

This file should have been added a few commits back already...

15 years agoExtract entities from the session and return them in the design file.
Matthijs Kooijman [Fri, 13 Feb 2009 11:37:19 +0000 (12:37 +0100)]
Extract entities from the session and return them in the design file.

15 years agoGenerate VHDL entity declarations.
Matthijs Kooijman [Fri, 13 Feb 2009 11:28:36 +0000 (12:28 +0100)]
Generate VHDL entity declarations.

These declarations are still without ports and with a name that might not
be unique, though.

15 years agoCreate an entity for each function.
Matthijs Kooijman [Fri, 13 Feb 2009 11:17:58 +0000 (12:17 +0100)]
Create an entity for each function.

The entity does not yet contain the actual VHDL entity, but does contain
the argument / result to port name map.

15 years agoStore signals in a map.
Matthijs Kooijman [Fri, 13 Feb 2009 10:11:33 +0000 (11:11 +0100)]
Store signals in a map.

This turns the list of Signals into a list of (sigid, SignalInfo), which
enables lookup by id.

15 years agoName signals in a function after flattening it.
Matthijs Kooijman [Fri, 13 Feb 2009 09:43:09 +0000 (10:43 +0100)]
Name signals in a function after flattening it.

15 years agoAdd a modFunc function to edit a function in the session.
Matthijs Kooijman [Fri, 13 Feb 2009 08:55:53 +0000 (09:55 +0100)]
Add a modFunc function to edit a function in the session.

15 years agoRemove NamedFlatFunction again.
Matthijs Kooijman [Fri, 13 Feb 2009 08:55:29 +0000 (09:55 +0100)]
Remove NamedFlatFunction again.

We'll use another way to represent names in FlatFunctions.

15 years agoAllow a FlatFunction to be named as well as unnamed.
Matthijs Kooijman [Wed, 11 Feb 2009 19:22:07 +0000 (20:22 +0100)]
Allow a FlatFunction to be named as well as unnamed.

15 years agoFill the signal list in FlatFunction.
Matthijs Kooijman [Wed, 11 Feb 2009 19:13:10 +0000 (20:13 +0100)]
Fill the signal list in FlatFunction.