Put some function names inside \hs.
authorMatthijs Kooijman <matthijs@stdin.nl>
Tue, 8 Dec 2009 15:33:37 +0000 (16:33 +0100)
committerMatthijs Kooijman <matthijs@stdin.nl>
Tue, 8 Dec 2009 15:33:37 +0000 (16:33 +0100)
Chapters/Prototype.tex

index 73873bd2d2fd0115a142713cd2210de3f63d79aa..390e98b57c39dc0a1da114a812bd4e8272d1967a 100644 (file)
         end architecture structural;
       \stopbuffer 
     
-      \placeexample[][ex:AvgStateTypes]{\VHDL\ types generated for acc and avg from \in{example}[ex:AvgState]}
+      \placeexample[][ex:AvgStateTypes]{\VHDL\ types generated for \hs{acc} and \hs{avg} from \in{example}[ex:AvgState]}
           {\typebuffervhdl{AvgStateTypes}}
-      \placeexample[][ex:AccStateVHDL]{\VHDL\ generated for acc from \in{example}[ex:AvgState]}
+      \placeexample[][ex:AccStateVHDL]{\VHDL\ generated for \hs{acc} from \in{example}[ex:AvgState]}
           {\typebuffervhdl{AccStateVHDL}}
-      \placeexample[][ex:AvgStateVHDL]{\VHDL\ generated for avg from \in{example}[ex:AvgState]}
+      \placeexample[][ex:AvgStateVHDL]{\VHDL\ generated for \hs{avg} from \in{example}[ex:AvgState]}
           {\typebuffervhdl{AvgStateVHDL}}
 %    \subsection{Initial state}
 %      How to specify the initial state? Cannot be done inside a hardware