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Put some function names inside \hs.
author
Matthijs Kooijman
<matthijs@stdin.nl>
Tue, 8 Dec 2009 15:33:37 +0000
(16:33 +0100)
committer
Matthijs Kooijman
<matthijs@stdin.nl>
Tue, 8 Dec 2009 15:33:37 +0000
(16:33 +0100)
Chapters/Prototype.tex
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diff --git
a/Chapters/Prototype.tex
b/Chapters/Prototype.tex
index 73873bd2d2fd0115a142713cd2210de3f63d79aa..390e98b57c39dc0a1da114a812bd4e8272d1967a 100644
(file)
--- a/
Chapters/Prototype.tex
+++ b/
Chapters/Prototype.tex
@@
-1424,11
+1424,11
@@
end architecture structural;
\stopbuffer
end architecture structural;
\stopbuffer
- \placeexample[][ex:AvgStateTypes]{\VHDL\ types generated for
acc and avg
from \in{example}[ex:AvgState]}
+ \placeexample[][ex:AvgStateTypes]{\VHDL\ types generated for
\hs{acc} and \hs{avg}
from \in{example}[ex:AvgState]}
{\typebuffervhdl{AvgStateTypes}}
{\typebuffervhdl{AvgStateTypes}}
- \placeexample[][ex:AccStateVHDL]{\VHDL\ generated for
acc
from \in{example}[ex:AvgState]}
+ \placeexample[][ex:AccStateVHDL]{\VHDL\ generated for
\hs{acc}
from \in{example}[ex:AvgState]}
{\typebuffervhdl{AccStateVHDL}}
{\typebuffervhdl{AccStateVHDL}}
- \placeexample[][ex:AvgStateVHDL]{\VHDL\ generated for
avg
from \in{example}[ex:AvgState]}
+ \placeexample[][ex:AvgStateVHDL]{\VHDL\ generated for
\hs{avg}
from \in{example}[ex:AvgState]}
{\typebuffervhdl{AvgStateVHDL}}
% \subsection{Initial state}
% How to specify the initial state? Cannot be done inside a hardware
{\typebuffervhdl{AvgStateVHDL}}
% \subsection{Initial state}
% How to specify the initial state? Cannot be done inside a hardware