{-# LINE 84 "PolyAlu.lhs" #-}
vectOp :: (a -> a -> a) -> Op s a
vectOp f a b = foldl f a b
-{-# LINE 96 "PolyAlu.lhs" #-}
+{-# LINE 99 "PolyAlu.lhs" #-}
alu ::
Op s a ->
Op s a ->
Opcode -> a -> Vector s a -> a
alu op1 op2 Low a b = op1 a b
alu op1 op2 High a b = op2 a b
-{-# LINE 112 "PolyAlu.lhs" #-}
+{-# LINE 118 "PolyAlu.lhs" #-}
registerBank ::
- ((NaturalT s ,PositiveT (s :+: D1),((s :+: D1) :>: s) ~ True )) =>
- (RegState s a) -> a -> RangedWord s ->
+ ((NaturalT s ,PositiveT (s :+: D1),((s :+: D1) :>: s) ~ True )) => (RegState s a) -> a -> RangedWord s ->
RangedWord s -> Bit -> ((RegState s a), a )
registerBank (State mem) data_in rdaddr wraddr wrenable =
data_out = mem!rdaddr
mem' | wrenable == Low = mem
| otherwise = replace mem wraddr data_in
-{-# LINE 133 "PolyAlu.lhs" #-}
+{-# LINE 141 "PolyAlu.lhs" #-}
{-# ANN actual_cpu TopEntity#-}
actual_cpu ::
(Opcode, Word, Vector D4 Word, RangedWord D9,
where
alu_out = alu (primOp (+)) (vectOp (+)) opc ram_out b
(ram',ram_out) = registerBank ram a rdaddr wraddr wren
-{-# LINE 149 "PolyAlu.lhs" #-}
+{-# LINE 160 "PolyAlu.lhs" #-}
{-# ANN initstate InitState#-}
initstate :: RegState D9 Word
initstate = State (copy (0 :: Word))