X-Git-Url: https://git.stderr.nl/gitweb?p=matthijs%2Fmaster-project%2Fhaskell-symposium-talk.git;a=blobdiff_plain;f=PolyAlu.hs;fp=PolyAlu.hs;h=21f6eff03f2516e9b834e154ec6fb28656e5d3fc;hp=23dfaa4fbe0fd47139e430f6ccfb1b2a47927efb;hb=2523b691bc4f9871e5d0fb3823fcd2c8952affaa;hpb=994fb60ca2fb9a48380e54b4392f7519fcc63ec1

diff --git a/PolyAlu.hs b/PolyAlu.hs
index 23dfaa4..21f6eff 100644
--- a/PolyAlu.hs
+++ b/PolyAlu.hs
@@ -21,17 +21,16 @@ primOp f a b = a `f` a
 {-# LINE 84 "PolyAlu.lhs" #-}
 vectOp :: (a -> a -> a) -> Op s a
 vectOp f a b = foldl f a b
-{-# LINE 96 "PolyAlu.lhs" #-}
+{-# LINE 99 "PolyAlu.lhs" #-}
 alu :: 
   Op s a -> 
   Op s a -> 
   Opcode -> a -> Vector s a -> a
 alu op1 op2 Low    a b = op1 a b
 alu op1 op2 High   a b = op2 a b
-{-# LINE 112 "PolyAlu.lhs" #-}
+{-# LINE 118 "PolyAlu.lhs" #-}
 registerBank :: 
-  ((NaturalT s ,PositiveT (s :+: D1),((s :+: D1) :>: s) ~ True )) =>
-  (RegState s a) -> a -> RangedWord s ->
+  ((NaturalT s ,PositiveT (s :+: D1),((s :+: D1) :>: s) ~ True )) => (RegState s a) -> a -> RangedWord s ->
   RangedWord s -> Bit -> ((RegState s a), a )
   
 registerBank (State mem) data_in rdaddr wraddr wrenable = 
@@ -40,7 +39,7 @@ registerBank (State mem) data_in rdaddr wraddr wrenable =
     data_out  =   mem!rdaddr
     mem'  | wrenable == Low    = mem
           | otherwise          = replace mem wraddr data_in
-{-# LINE 133 "PolyAlu.lhs" #-}
+{-# LINE 141 "PolyAlu.lhs" #-}
 {-# ANN actual_cpu TopEntity#-}
 actual_cpu :: 
   (Opcode, Word, Vector D4 Word, RangedWord D9, 
@@ -51,7 +50,7 @@ actual_cpu (opc, a ,b, rdaddr, wraddr, wren) ram = (ram', alu_out)
   where
     alu_out = alu (primOp (+)) (vectOp (+)) opc ram_out b
     (ram',ram_out)  = registerBank ram a rdaddr wraddr wren
-{-# LINE 149 "PolyAlu.lhs" #-}
+{-# LINE 160 "PolyAlu.lhs" #-}
 {-# ANN initstate InitState#-}
 initstate :: RegState D9 Word
 initstate = State (copy (0 :: Word))