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Complete draft version of the presentation
[matthijs/master-project/haskell-symposium-talk.git]
/
PolyAlu.hs
diff --git
a/PolyAlu.hs
b/PolyAlu.hs
index 23dfaa4fbe0fd47139e430f6ccfb1b2a47927efb..21f6eff03f2516e9b834e154ec6fb28656e5d3fc 100644
(file)
--- a/
PolyAlu.hs
+++ b/
PolyAlu.hs
@@
-21,17
+21,16
@@
primOp f a b = a `f` a
{-# LINE 84 "PolyAlu.lhs" #-}
vectOp :: (a -> a -> a) -> Op s a
vectOp f a b = foldl f a b
{-# LINE 84 "PolyAlu.lhs" #-}
vectOp :: (a -> a -> a) -> Op s a
vectOp f a b = foldl f a b
-{-# LINE 9
6
"PolyAlu.lhs" #-}
+{-# LINE 9
9
"PolyAlu.lhs" #-}
alu ::
Op s a ->
Op s a ->
Opcode -> a -> Vector s a -> a
alu op1 op2 Low a b = op1 a b
alu op1 op2 High a b = op2 a b
alu ::
Op s a ->
Op s a ->
Opcode -> a -> Vector s a -> a
alu op1 op2 Low a b = op1 a b
alu op1 op2 High a b = op2 a b
-{-# LINE 11
2
"PolyAlu.lhs" #-}
+{-# LINE 11
8
"PolyAlu.lhs" #-}
registerBank ::
registerBank ::
- ((NaturalT s ,PositiveT (s :+: D1),((s :+: D1) :>: s) ~ True )) =>
- (RegState s a) -> a -> RangedWord s ->
+ ((NaturalT s ,PositiveT (s :+: D1),((s :+: D1) :>: s) ~ True )) => (RegState s a) -> a -> RangedWord s ->
RangedWord s -> Bit -> ((RegState s a), a )
registerBank (State mem) data_in rdaddr wraddr wrenable =
RangedWord s -> Bit -> ((RegState s a), a )
registerBank (State mem) data_in rdaddr wraddr wrenable =
@@
-40,7
+39,7
@@
registerBank (State mem) data_in rdaddr wraddr wrenable =
data_out = mem!rdaddr
mem' | wrenable == Low = mem
| otherwise = replace mem wraddr data_in
data_out = mem!rdaddr
mem' | wrenable == Low = mem
| otherwise = replace mem wraddr data_in
-{-# LINE 1
33
"PolyAlu.lhs" #-}
+{-# LINE 1
41
"PolyAlu.lhs" #-}
{-# ANN actual_cpu TopEntity#-}
actual_cpu ::
(Opcode, Word, Vector D4 Word, RangedWord D9,
{-# ANN actual_cpu TopEntity#-}
actual_cpu ::
(Opcode, Word, Vector D4 Word, RangedWord D9,
@@
-51,7
+50,7
@@
actual_cpu (opc, a ,b, rdaddr, wraddr, wren) ram = (ram', alu_out)
where
alu_out = alu (primOp (+)) (vectOp (+)) opc ram_out b
(ram',ram_out) = registerBank ram a rdaddr wraddr wren
where
alu_out = alu (primOp (+)) (vectOp (+)) opc ram_out b
(ram',ram_out) = registerBank ram a rdaddr wraddr wren
-{-# LINE 1
49
"PolyAlu.lhs" #-}
+{-# LINE 1
60
"PolyAlu.lhs" #-}
{-# ANN initstate InitState#-}
initstate :: RegState D9 Word
initstate = State (copy (0 :: Word))
{-# ANN initstate InitState#-}
initstate :: RegState D9 Word
initstate = State (copy (0 :: Word))