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Add reference to Haskell and Verilog. Add something about state to introduction
authorChristiaan Baaij <baaijcpr@wlan229203.mobiel.utwente.nl>
Thu, 11 Feb 2010 11:31:42 +0000 (12:31 +0100)
committerChristiaan Baaij <baaijcpr@wlan229203.mobiel.utwente.nl>
Thu, 11 Feb 2010 11:31:42 +0000 (12:31 +0100)

No differences found
Paper intended for DSD 2010