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Add reference to Haskell and Verilog. Add something about state to introduction
[matthijs/master-project/dsd-paper.git]
/
Makefile
1
all:
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latexmk -r latexmkrc -pdf -pvc cλash.lhs
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clean:
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latexmk -CA
projects / matthijs / master-project / dsd-paper.git / blob