Redo the global (state) structure of the translator.
[matthijs/master-project/cλash.git] / VHDL.hs
2009-03-10 Matthijs KooijmanRedo the global (state) structure of the translator.
2009-03-09 Matthijs KooijmanUse Data.Accessor for FuncData.
2009-03-09 Matthijs KooijmanRemove createArchitecture from the VHDLState Monad.
2009-03-09 Matthijs KooijmanRemove mkConcSm from the VHDLState monad.
2009-03-09 Matthijs KooijmanMake createEntity preserve the Entity on builtin functions.
2009-03-05 Matthijs KooijmanRemove createEntity from the VHDLState monad.
2009-03-05 Matthijs KooijmanRemove getDesignFiles from the VHDLState monad.
2009-03-05 Matthijs KooijmanStrip adjacent underscores from VHDLIds.
2009-03-04 Matthijs KooijmanProvide preliminary support for list types.
2009-03-04 Matthijs KooijmanMap the clk port on stateful function applications.
2009-03-03 Matthijs KooijmanLet VHDL use SignalInfo instead of HsFunction for gener...
2009-02-19 Matthijs KooijmanWrite each VHDL entity to a seperate file.
2009-02-19 Matthijs KooijmanAlso allow uppercase letters and a period in VHDL ids.
2009-02-19 Matthijs KooijmanStrip invalid characters from VHDL identifiers.
2009-02-19 Matthijs KooijmanEnable the DontCare value for Bit again.
2009-02-19 Matthijs KooijmanMake register_bank work, with a bunch of changes.
2009-02-19 Matthijs KooijmanSupport multiple alternative case expressions.
2009-02-18 Matthijs KooijmanGenerate VHDL for UncondDefs.
2009-02-17 Matthijs KooijmanGeneralize FApp and CondDef into SigDef and add UncondDef.
2009-02-17 Matthijs KooijmanAdd a type alias StateId for state numbers.
2009-02-17 Matthijs KooijmanRemove type parameterisation of SignalMap.
2009-02-17 Matthijs KooijmanDon't generate ports for non-port signals.
2009-02-17 Matthijs KooijmanGenerate VHDL signals for internal signals and state.
2009-02-17 Matthijs KooijmanAlways import IEEE.std_logic_1164 in the generated...
2009-02-17 Matthijs KooijmanMove the DesignFile creation to VHDL.
2009-02-17 Matthijs KooijmanAdd clk port on any stateful entity.
2009-02-17 Matthijs KooijmanCreate state procs for state signals.
2009-02-16 Matthijs KooijmanAdd port maps to component instantiations.
2009-02-16 Matthijs KooijmanMake application names unique.
2009-02-16 Matthijs KooijmanLet mkCompInsSm look up the actual VHDL entity id.
2009-02-16 Matthijs KooijmanPut mkCompInsSm in the VHDLState monad.
2009-02-13 Matthijs KooijmanMake modFuncs work with stateful functions.
2009-02-13 Matthijs KooijmanGenerate dummy component instantiations for each archit...
2009-02-13 Matthijs KooijmanUse less general names as labels some fields.
2009-02-13 Matthijs KooijmanGenerate a VHDL architecture for each function.
2009-02-13 Matthijs KooijmanAdd port declarations to the VHDL entities.
2009-02-13 Matthijs KooijmanPut a TypeMark in a VHDLSignalmap.
2009-02-13 Matthijs KooijmanRename fields of SignalInfo.
2009-02-13 Matthijs KooijmanExtract entities from the session and return them in...
2009-02-13 Matthijs KooijmanGenerate VHDL entity declarations.
2009-02-13 Matthijs KooijmanCreate an entity for each function.
2009-02-13 Matthijs KooijmanRemove NamedFlatFunction again.
2009-02-11 Matthijs KooijmanMove around a bunch of types.
2009-02-11 Matthijs KooijmanGreatly clean up Translator.