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[matthijs/master-project/cλash.git] / VHDL.hs

2009-02-19	Matthijs Kooijman	Enable the DontCare value for Bit again.	blob \| commitdiff \| raw
2009-02-19	Matthijs Kooijman	Make register_bank work, with a bunch of changes.	blob \| commitdiff \| raw \| diff to current
2009-02-19	Matthijs Kooijman	Support multiple alternative case expressions.	blob \| commitdiff \| raw \| diff to current
2009-02-18	Matthijs Kooijman	Generate VHDL for UncondDefs.	blob \| commitdiff \| raw \| diff to current
2009-02-17	Matthijs Kooijman	Generalize FApp and CondDef into SigDef and add UncondDef.	blob \| commitdiff \| raw \| diff to current
2009-02-17	Matthijs Kooijman	Add a type alias StateId for state numbers.	blob \| commitdiff \| raw \| diff to current
2009-02-17	Matthijs Kooijman	Remove type parameterisation of SignalMap.	blob \| commitdiff \| raw \| diff to current
2009-02-17	Matthijs Kooijman	Don't generate ports for non-port signals.	blob \| commitdiff \| raw \| diff to current
2009-02-17	Matthijs Kooijman	Generate VHDL signals for internal signals and state.	blob \| commitdiff \| raw \| diff to current
2009-02-17	Matthijs Kooijman	Always import IEEE.std_logic_1164 in the generated...	blob \| commitdiff \| raw \| diff to current
2009-02-17	Matthijs Kooijman	Move the DesignFile creation to VHDL.	blob \| commitdiff \| raw \| diff to current
2009-02-17	Matthijs Kooijman	Add clk port on any stateful entity.	blob \| commitdiff \| raw \| diff to current
2009-02-17	Matthijs Kooijman	Create state procs for state signals.	blob \| commitdiff \| raw \| diff to current
2009-02-16	Matthijs Kooijman	Add port maps to component instantiations.	blob \| commitdiff \| raw \| diff to current
2009-02-16	Matthijs Kooijman	Make application names unique.	blob \| commitdiff \| raw \| diff to current
2009-02-16	Matthijs Kooijman	Let mkCompInsSm look up the actual VHDL entity id.	blob \| commitdiff \| raw \| diff to current
2009-02-16	Matthijs Kooijman	Put mkCompInsSm in the VHDLState monad.	blob \| commitdiff \| raw \| diff to current
2009-02-13	Matthijs Kooijman	Make modFuncs work with stateful functions.	blob \| commitdiff \| raw \| diff to current
2009-02-13	Matthijs Kooijman	Generate dummy component instantiations for each archit...	blob \| commitdiff \| raw \| diff to current
2009-02-13	Matthijs Kooijman	Use less general names as labels some fields.	blob \| commitdiff \| raw \| diff to current
2009-02-13	Matthijs Kooijman	Generate a VHDL architecture for each function.	blob \| commitdiff \| raw \| diff to current
2009-02-13	Matthijs Kooijman	Add port declarations to the VHDL entities.	blob \| commitdiff \| raw \| diff to current
2009-02-13	Matthijs Kooijman	Put a TypeMark in a VHDLSignalmap.	blob \| commitdiff \| raw \| diff to current
2009-02-13	Matthijs Kooijman	Rename fields of SignalInfo.	blob \| commitdiff \| raw \| diff to current
2009-02-13	Matthijs Kooijman	Extract entities from the session and return them in...	blob \| commitdiff \| raw \| diff to current
2009-02-13	Matthijs Kooijman	Generate VHDL entity declarations.	blob \| commitdiff \| raw \| diff to current
2009-02-13	Matthijs Kooijman	Create an entity for each function.	blob \| commitdiff \| raw \| diff to current
2009-02-13	Matthijs Kooijman	Remove NamedFlatFunction again.	blob \| commitdiff \| raw \| diff to current
2009-02-11	Matthijs Kooijman	Move around a bunch of types.	blob \| commitdiff \| raw \| diff to current
2009-02-11	Matthijs Kooijman	Greatly clean up Translator.	blob \| commitdiff \| raw \| diff to current

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