Add clk port on any stateful entity.
[matthijs/master-project/cλash.git] / VHDL.hs
2009-02-17 Matthijs KooijmanAdd clk port on any stateful entity.
2009-02-17 Matthijs KooijmanCreate state procs for state signals.
2009-02-16 Matthijs KooijmanAdd port maps to component instantiations.
2009-02-16 Matthijs KooijmanMake application names unique.
2009-02-16 Matthijs KooijmanLet mkCompInsSm look up the actual VHDL entity id.
2009-02-16 Matthijs KooijmanPut mkCompInsSm in the VHDLState monad.
2009-02-13 Matthijs KooijmanMake modFuncs work with stateful functions.
2009-02-13 Matthijs KooijmanGenerate dummy component instantiations for each archit...
2009-02-13 Matthijs KooijmanUse less general names as labels some fields.
2009-02-13 Matthijs KooijmanGenerate a VHDL architecture for each function.
2009-02-13 Matthijs KooijmanAdd port declarations to the VHDL entities.
2009-02-13 Matthijs KooijmanPut a TypeMark in a VHDLSignalmap.
2009-02-13 Matthijs KooijmanRename fields of SignalInfo.
2009-02-13 Matthijs KooijmanExtract entities from the session and return them in...
2009-02-13 Matthijs KooijmanGenerate VHDL entity declarations.
2009-02-13 Matthijs KooijmanCreate an entity for each function.
2009-02-13 Matthijs KooijmanRemove NamedFlatFunction again.
2009-02-11 Matthijs KooijmanMove around a bunch of types.
2009-02-11 Matthijs KooijmanGreatly clean up Translator.