matthijs/master-project/cλash.git
2009-04-06 Matthijs KooijmanIgnore .swp files.
2009-04-06 Matthijs KooijmanAdd the new HsTools module.
2009-04-06 Matthijs KooijmanAdd the new GhcTools module.
2009-04-06 Matthijs KooijmanCleanup imports and add a vim modeline.
2009-04-06 Matthijs KooijmanMake listBind also show the type of the bind.
2009-04-06 Matthijs KooijmanDerive Show for more types.
2009-04-02 Matthijs KooijmanDelete unused Parser.hs.
2009-03-10 Matthijs KooijmanAdd a TODO.
2009-03-10 Matthijs KooijmanRemove a few stale TODOs.
2009-03-10 Matthijs KooijmanImport the ieee library into the generated types package.
2009-03-10 Matthijs KooijmanFilter out dots from generated type id's.
2009-03-10 Matthijs KooijmanPut vhdl_ty in the (new) TypeState Monad.
2009-03-10 Matthijs KooijmanOutput a package containing all type declarations.
2009-03-10 Matthijs KooijmanAdd support for builtin functions again.
2009-03-10 Matthijs KooijmanRedo the global (state) structure of the translator.
2009-03-09 Matthijs KooijmanRename VHDLState to TranslatorState.
2009-03-09 Matthijs KooijmanUse Data.Accessor for FuncData.
2009-03-09 Matthijs KooijmanRemove createArchitecture from the VHDLState Monad.
2009-03-09 Matthijs KooijmanRemove mkConcSm from the VHDLState monad.
2009-03-09 Matthijs KooijmanRemove nameFlatFunction from the VHDLState monad.
2009-03-09 Matthijs KooijmanMake createEntity preserve the Entity on builtin functions.
2009-03-06 Matthijs KooijmanAdd a getFuncMap accessor for VHDLState.
2009-03-06 Matthijs KooijmanDerive Show for a bunch of types.
2009-03-06 Matthijs KooijmanMove the Show deriving for Core types to a new CoreShow...
2009-03-05 Matthijs KooijmanRemove the dontcare function from Bits.
2009-03-05 Matthijs KooijmanRemove createEntity from the VHDLState monad.
2009-03-05 Matthijs KooijmanRemove getDesignFiles from the VHDLState monad.
2009-03-05 Matthijs KooijmanStrip adjacent underscores from VHDLIds.
2009-03-04 Matthijs KooijmanProvide preliminary support for list types.
2009-03-04 Matthijs KooijmanAdd some hardware models using vectors (FSVec).
2009-03-04 Matthijs KooijmanFix propagateState removing all non-FApp SigDefs.
2009-03-04 Matthijs KooijmanMap the clk port on stateful function applications.
2009-03-04 Matthijs KooijmanDon't inline alu.
2009-03-04 Matthijs KooijmanRemove support for DontCare.
2009-03-03 Matthijs KooijmanFill in propagateState.
2009-03-03 Matthijs KooijmanRemove the now obsolete getOwnStates.
2009-03-03 Matthijs KooijmanAdd some predicates and accessors to FlattenTypes.
2009-03-03 Matthijs KooijmanLet VHDL use SignalInfo instead of HsFunction for gener...
2009-03-03 Matthijs KooijmanAdd initial (dummy) propagateState function.
2009-03-03 Matthijs KooijmanAdd vim modeline.
2009-03-03 Matthijs KooijmanAdd a is_FApp predicate.
2009-03-03 Matthijs KooijmanNever inline the half_adder function.
2009-03-03 Matthijs KooijmanAdd StandalonDeriving language option to Pretty.
2009-03-03 Matthijs KooijmanDon't add duplicate name hints.
2009-03-03 Matthijs KooijmanPut VHDL files for each design in a separate directory.
2009-03-03 Matthijs KooijmanAllow for generating VHDL for stateless functions.
2009-02-27 Matthijs KooijmanAdd some newlines in the output.
2009-02-27 Matthijs KooijmanMake exec have a single binding.
2009-02-27 Matthijs KooijmanAdd a two-port mux hardware model.
2009-02-19 Matthijs KooijmanWrite each VHDL entity to a seperate file.
2009-02-19 Matthijs KooijmanLet the exec function output something.
2009-02-19 Matthijs KooijmanSupport construction of empty tuples.
2009-02-19 Matthijs KooijmanPrint the list of signals sorted by id.
2009-02-19 Matthijs KooijmanAlso allow uppercase letters and a period in VHDL ids.
2009-02-19 Matthijs KooijmanAdd name hints to various signals generated.
2009-02-19 Matthijs KooijmanStrip invalid characters from VHDL identifiers.
2009-02-19 Matthijs KooijmanUse the name hints in signal name construction.
2009-02-19 Matthijs KooijmanDo the naming of a signal in named function instead...
2009-02-19 Matthijs KooijmanAllow name hints to be set for a signal.
2009-02-19 Matthijs KooijmanEnable the DontCare value for Bit again.
2009-02-19 Matthijs KooijmanPrint the Defs list sorted.
2009-02-19 Matthijs KooijmanMake register_bank work, with a bunch of changes.
2009-02-19 Matthijs KooijmanLet zipValueMapsWith show the trees in the error.
2009-02-19 Matthijs KooijmanUse tuples instead of a ADT for the register bank state.
2009-02-19 Matthijs KooijmanAdd space in error message.
2009-02-19 Matthijs KooijmanMake listBind also show a pretty printed output.
2009-02-19 Matthijs KooijmanFurther reduce main and add a makeVHDL function.
2009-02-19 Matthijs KooijmanSupport multiple alternative case expressions.
2009-02-19 Matthijs KooijmanAdd stateful alu (with empty state).
2009-02-18 Matthijs KooijmanAdd a simple four-bit shift register model.
2009-02-18 Matthijs KooijmanUse a different approach for marking SigUses.
2009-02-18 Matthijs KooijmanAdd setSignalInfo accessor for FlattenState.
2009-02-18 Matthijs KooijmanGenerate VHDL for UncondDefs.
2009-02-18 Matthijs KooijmanAdd a getSignalInfo accessor.
2009-02-18 Matthijs KooijmanAdd a listBind function to show the Core for a bind.
2009-02-18 Matthijs KooijmanSplit out the large main function a bit.
2009-02-18 Matthijs KooijmanRemove the DontCare value from the Bit type.
2009-02-18 Matthijs KooijmanDerive and use show instead of ppr to display Exprs.
2009-02-18 Matthijs KooijmanFix comment indent.
2009-02-17 Matthijs KooijmanGeneralize FApp and CondDef into SigDef and add UncondDef.
2009-02-17 Matthijs KooijmanAdd a type alias StateId for state numbers.
2009-02-17 Matthijs KooijmanRemove type parameterisation of SignalMap.
2009-02-17 Matthijs KooijmanDon't generate ports for non-port signals.
2009-02-17 Matthijs KooijmanGenerate VHDL signals for internal signals and state.
2009-02-17 Matthijs KooijmanAdd predicates for SigUse.
2009-02-17 Matthijs KooijmanMark all signals as ports or states when appropriate.
2009-02-17 Matthijs KooijmanAlways import IEEE.std_logic_1164 in the generated...
2009-02-17 Matthijs KooijmanMove the DesignFile creation to VHDL.
2009-02-17 Matthijs KooijmanAdd clk port on any stateful entity.
2009-02-17 Matthijs KooijmanCreate state procs for state signals.
2009-02-16 Matthijs KooijmanMark port signals as such during flattening.
2009-02-16 Matthijs KooijmanImprove the pretty output of the signal list.
2009-02-16 Matthijs KooijmanMake the pretty output more pretty.
2009-02-16 Matthijs KooijmanReduce genSignals to a single line using Traversable.
2009-02-16 Matthijs KooijmanStore a use for each signal in a flattened function.
2009-02-16 Matthijs KooijmanAdd port maps to component instantiations.
2009-02-16 Matthijs KooijmanMake application names unique.
2009-02-16 Matthijs KooijmanAdd Entities for builtin functions.
2009-02-16 Matthijs KooijmanLet mkCompInsSm look up the actual VHDL entity id.
2009-02-16 Matthijs KooijmanPut mkCompInsSm in the VHDLState monad.
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