Christiaan Baaij [Mon, 22 Jun 2009 10:22:31 +0000 (12:22 +0200)]
Added subtype declarations to TypeMap, removed SubtypeMap.
Merge branch 'cλash' of http://git.stderr.nl/matthijs/projects/master-project
* 'cλash' of http://git.stderr.nl/matthijs/projects/master-project: (32 commits)
Support application of dataconstructors.
Make mkAssign support assigning to a VHDLName as well.
Split off record field selection AST construction.
Only try to generate builtin functions for global binders.
Never try to normalize global binders.
Split off assignment generating code.
Support single-alt selector case expressions.
Add pprString convenience method.
Support single-constructor algebraic types.
Move type registration out of construct_vhdl_ty.
Split off the VHDL type generating code.
Actually use the introduced let from a few commits back...
Error out when normalizing polymorphic functions.
Add an empty let before starting normalization.
Add and use a mkFunction utility function.
Make beta reduction of Case expressions work for type arguments.
Add function propagation transform.
Improve debug output timing.
Don't propagate types with free tyvars.
Add is_applicable predicate.
...
Only try to generate builtin functions for global binders.
Since builtin functions will always come from elsewhere, these will
always be global. Functions for which we can generate components, on the
other hand, will always be local.
Previously, there was some duplicate AST building code for assignments in
mkConcSm. This is not split of into mkAssign, mkUncondAssign and
mkCondAssign.
construct_vhdl_ty now only creates the type and does not register it in
the session. Additionally, we save only the TypeDef in the session instead
of the TypeDec, since the latter contains the VHDLId which we also store
separately. This means we'll create the TypeDecs later, when outputint the
types VHDL package.
Previously, the vhdl_ty function did builtin type lookups, cached custom
types and creating new custom types. Now, the latter is moved into the new
function create_vhdl_ty.
This ensures that every expression will always contain a let at the top
level, since none of the transforms will remove the last let (lets are
only merged when two are nested).
This function creates a new function with a given body and adds it to the
TransformMonad state. The function is named after an existing binder, but
with a new Unique.
Make beta reduction of Case expressions work for type arguments.
Previously, splitFunTy was used, which assumes a function type, while a
type argument is applied to a forall type instead of a function type.
Using applyTypeToArg handles all this for us.
Any free type variables in a type argument wouldn't be in scope in the new
function. Eventually, beta reducation and applicable inlining should make
sure that all type variables are resolved.
This transform propagates type arguments passed to functions into (a copy
of) the called function, effectively removing all type arguments. This is
the first cross-function transformation pass.
This allows for functions to use other (user-defined) functions, which
will then also get VHDL generated. Also restructures some code to make
this possible. In particular, the TranslatorState is now no longer used
(but not yet removed).
Christiaan Baaij [Fri, 19 Jun 2009 11:25:24 +0000 (13:25 +0200)]
Merge branch 'cλash' of http://git.stderr.nl/matthijs/projects/master-project
* 'cλash' of http://git.stderr.nl/matthijs/projects/master-project:
Add another higher order testcase, highordtest2.
Support VHDL generation for two-alternative cases.
Support VHDL generation for two-alternative cases.
This does not support single alternatives statements yet, and will never
support more than two alternatives. Only supports case statements on Bit
and Bool types for now.
Christiaan Baaij [Fri, 19 Jun 2009 10:17:44 +0000 (12:17 +0200)]
Merge branch 'cλash' of http://git.stderr.nl/matthijs/projects/master-project
* 'cλash' of http://git.stderr.nl/matthijs/projects/master-project:
Use highordtest in main, since that can now be normalized.
Add a (fairly complete) set of transforms.
Add is_lam and is_fun predicates.
Add a inlinebind helper function.
Add a substitute helper function.
Print the type in the transform debug output.
Add infrastructure for running core to core transformations.
Add a higher order testcase.
Add is_wild function to check for wild binders.
Generate VHDL from Core instead of flat functions.
Generate VHDL from Core instead of flat functions.
This bypasses all of the Flatten functionality for now and generates VHDL
directly. The generation only works on very simple Core programs, that are
already in normal form. An example of such a program is the inv function
in Adders.hs.
For now, all state generation is broken again. Support for ValueMaps has
mostly been removed, since in the future tuples will be translated to
records in VHDL instead of being flattened.
This allows callers to put any number of modules into scope before
translating to Core. Previously, functions and values could be
automatically imported by using their qualified name, but now also
instances can be used from modules that would not be imported otherwise.
This function allows us to import a module inside the TcRn monad and
properly handles (family) instances. This is needed for working with the
tfp package.
This module will contain functions to work with specific constructs
represented as Core expressions and types (i.e., it knows about how
certain libraries are structured and uses functions from there).
For now, this contains a single function to translate (the Core
representation of) a type level int from the tfp package to a real Int.
In particular, this derives Show for all Outputable types, which requires
some ugly language pragma's (UndecidableTypes...). However, now HsExpr as
well as Type should be decently showable.