matthijs/master-project/cλash.git
15 years agoIndex the list of functions with information about argument usage in addition to...
Matthijs Kooijman [Mon, 2 Feb 2009 12:11:01 +0000 (13:11 +0100)]
Index the list of functions with information about argument usage in addition to the function name.

This will allow some sort of function overloading later on. In particular,
it will allow the VHDL interface and implementation of a function be
different depending on how and where the function is called, but still use
the same VHDL entity where the invocations are the same.

The extra information is not yet used or filled in, this will come next.

15 years agoIntroduce a new type HsValueMap.
Matthijs Kooijman [Mon, 2 Feb 2009 11:44:50 +0000 (12:44 +0100)]
Introduce a new type HsValueMap.

This type generalized SignalNameMap (which remains as a type alias for
now), but can map a haskell value to any value.

15 years agoMake tuple construction handling more portable.
Matthijs Kooijman [Mon, 2 Feb 2009 11:17:26 +0000 (12:17 +0100)]
Make tuple construction handling more portable.

15 years agoRemove the getInstantiations function.
Matthijs Kooijman [Mon, 2 Feb 2009 11:07:41 +0000 (12:07 +0100)]
Remove the getInstantiations function.

It was no longer used and replaced by expandExpr.

15 years agoWrite the resulting vhdl to file.
Matthijs Kooijman [Mon, 2 Feb 2009 09:01:37 +0000 (10:01 +0100)]
Write the resulting vhdl to file.

15 years agoReplace - with _ in VHDL ids.
Matthijs Kooijman [Mon, 2 Feb 2009 09:01:19 +0000 (10:01 +0100)]
Replace - with _ in VHDL ids.

15 years agoSet VHDL types based on Haskell Types.
Matthijs Kooijman [Fri, 30 Jan 2009 12:40:30 +0000 (13:40 +0100)]
Set VHDL types based on Haskell Types.

Only the Bit type is supported so far.

15 years agoStore the type of a signal in a SignalNameMap.
Matthijs Kooijman [Fri, 30 Jan 2009 12:21:07 +0000 (13:21 +0100)]
Store the type of a signal in a SignalNameMap.

Note that the type is still always filled with vhdl_bit_ty, but this moves
this hardcoding from two seperate places to one place (where we can remove
it next).

15 years agoMake SignalNameMap always map VHDLId's.
Matthijs Kooijman [Fri, 30 Jan 2009 12:13:18 +0000 (13:13 +0100)]
Make SignalNameMap always map VHDLId's.

Previously, the SignalNameMap had a type argument to specify the
idenitifier type, which helped in transitioning from String to VHDLId but
is not longer used now.

15 years agoGenerate entities in addition to architectures.
Matthijs Kooijman [Fri, 30 Jan 2009 12:02:46 +0000 (13:02 +0100)]
Generate entities in addition to architectures.

15 years agoStore the VHDLId of a function in HWFunction.
Matthijs Kooijman [Fri, 30 Jan 2009 11:31:29 +0000 (12:31 +0100)]
Store the VHDLId of a function in HWFunction.

15 years agoGive Adders a mainIO to to interactive simulation.
Matthijs Kooijman [Fri, 30 Jan 2009 09:29:45 +0000 (10:29 +0100)]
Give Adders a mainIO to to interactive simulation.

15 years agoAdd a a new function "stateless".
Matthijs Kooijman [Fri, 30 Jan 2009 09:25:15 +0000 (10:25 +0100)]
Add a a new function "stateless".

This function converts a stateless circuit into a stateful one (with an
empty state), so it can be simulated.

15 years agoAdd a stateless circuit type.
Matthijs Kooijman [Fri, 30 Jan 2009 09:23:49 +0000 (10:23 +0100)]
Add a stateless circuit type.

15 years agoRename the Circuit type to SCircuit (for stateful)
Matthijs Kooijman [Fri, 30 Jan 2009 09:14:42 +0000 (10:14 +0100)]
Rename the Circuit type to SCircuit (for stateful)

15 years agoRename a bunch of type variables.
Matthijs Kooijman [Fri, 30 Jan 2009 09:13:45 +0000 (10:13 +0100)]
Rename a bunch of type variables.

15 years agoStore the RegisterBankState in a algbraic data type.
Matthijs Kooijman [Fri, 30 Jan 2009 09:11:06 +0000 (10:11 +0100)]
Store the RegisterBankState in a algbraic data type.

15 years agoShow input on each simulation step.
Matthijs Kooijman [Fri, 30 Jan 2009 09:10:41 +0000 (10:10 +0100)]
Show input on each simulation step.

15 years agoPrint the binds we're about to translate.
Matthijs Kooijman [Fri, 30 Jan 2009 08:56:27 +0000 (09:56 +0100)]
Print the binds we're about to translate.

15 years agoImplement full_adder in terms of half_adder.
Matthijs Kooijman [Fri, 30 Jan 2009 08:55:44 +0000 (09:55 +0100)]
Implement full_adder in terms of half_adder.

15 years agoAllow multiple functions to be translated in the same session.
Matthijs Kooijman [Thu, 29 Jan 2009 16:55:24 +0000 (17:55 +0100)]
Allow multiple functions to be translated in the same session.

15 years agoSwap argument order on findBind.
Matthijs Kooijman [Thu, 29 Jan 2009 16:47:45 +0000 (17:47 +0100)]
Swap argument order on findBind.

15 years agoLearn expandExpr how to handle Let expressions.
Matthijs Kooijman [Thu, 29 Jan 2009 16:43:32 +0000 (17:43 +0100)]
Learn expandExpr how to handle Let expressions.

15 years agoMake full_adder simpler.
Matthijs Kooijman [Thu, 29 Jan 2009 16:43:10 +0000 (17:43 +0100)]
Make full_adder simpler.

15 years agoImprove error message for createSignalAssignments.
Matthijs Kooijman [Thu, 29 Jan 2009 16:42:42 +0000 (17:42 +0100)]
Improve error message for createSignalAssignments.

15 years agoLearn ExpandExpr how to handle simple case expressions.
Matthijs Kooijman [Thu, 29 Jan 2009 16:42:09 +0000 (17:42 +0100)]
Learn ExpandExpr how to handle simple case expressions.

15 years agoAdd a base case to splitTupleConstructorArgs.
Matthijs Kooijman [Thu, 29 Jan 2009 15:49:05 +0000 (16:49 +0100)]
Add a base case to splitTupleConstructorArgs.

Apparently we've never tried to find the end of the returned list before :-)

15 years agoLearn expandExpr how to handle tuple construction.
Matthijs Kooijman [Thu, 29 Jan 2009 15:48:30 +0000 (16:48 +0100)]
Learn expandExpr how to handle tuple construction.

15 years agoAdd a duplication hardware model.
Matthijs Kooijman [Thu, 29 Jan 2009 15:48:03 +0000 (16:48 +0100)]
Add a duplication hardware model.

15 years agoImplement expandArgs in terms of expandExpr.
Matthijs Kooijman [Thu, 29 Jan 2009 15:32:09 +0000 (16:32 +0100)]
Implement expandArgs in terms of expandExpr.

This makes expandArgs a lot more general.

15 years agoAdd a double invertor model.
Matthijs Kooijman [Thu, 29 Jan 2009 15:31:31 +0000 (16:31 +0100)]
Add a double invertor model.

15 years agoLearn expandExpr how to expand Application.
Matthijs Kooijman [Thu, 29 Jan 2009 15:21:12 +0000 (16:21 +0100)]
Learn expandExpr how to expand Application.

15 years agoLet expandExpr error out on unsupported expressions.
Matthijs Kooijman [Thu, 29 Jan 2009 14:32:32 +0000 (15:32 +0100)]
Let expandExpr error out on unsupported expressions.

15 years agoAdd an invertor hardware model.
Matthijs Kooijman [Thu, 29 Jan 2009 14:32:09 +0000 (15:32 +0100)]
Add an invertor hardware model.

15 years agoRework the VHDL generation to be more bottom up.
Matthijs Kooijman [Thu, 29 Jan 2009 14:26:35 +0000 (15:26 +0100)]
Rework the VHDL generation to be more bottom up.

The new function expandExpr does something similar to getInstantiations
(and is used instead of it now), but follows a more bottom up approach,
generating new signals as needed and only connecting these signals to
ports at the very end. This allows for more general handling of nested
expressions and will probably make things less complex.

For now, this means that the Translator can only translate the trivial
"wire" hardware model, more support coming up.

This also means that we're using VHDLId's in almost all SignalNameMaps
now, which reduced the conversion from String.

15 years agoAdd a trivial "wire" hardware model.
Matthijs Kooijman [Thu, 29 Jan 2009 14:22:35 +0000 (15:22 +0100)]
Add a trivial "wire" hardware model.

15 years agoRename PortNameMap to SignalNameMap and make it a dependent type.
Matthijs Kooijman [Thu, 29 Jan 2009 12:29:07 +0000 (13:29 +0100)]
Rename PortNameMap to SignalNameMap and make it a dependent type.

15 years agoMove around some functionality.
Matthijs Kooijman [Thu, 29 Jan 2009 12:16:47 +0000 (13:16 +0100)]
Move around some functionality.

This moves some code from getPortMapEntry into a new function expandArgs,
and also prepares for generating signal declarations in addition to
component instantiations.

15 years agoReorder and comment things a bit.
Matthijs Kooijman [Thu, 29 Jan 2009 11:26:29 +0000 (12:26 +0100)]
Reorder and comment things a bit.

15 years agoUse uniqueName to make component instantiations unique.
Matthijs Kooijman [Thu, 29 Jan 2009 10:43:18 +0000 (11:43 +0100)]
Use uniqueName to make component instantiations unique.

15 years agoAdd a uniqueName function.
Matthijs Kooijman [Thu, 29 Jan 2009 10:42:50 +0000 (11:42 +0100)]
Add a uniqueName function.

This function appends a unique number to names to make the names unique.

15 years agoAdd some comments.
Matthijs Kooijman [Thu, 29 Jan 2009 10:36:34 +0000 (11:36 +0100)]
Add some comments.

15 years agoUse spaces instead of tabs.
Matthijs Kooijman [Tue, 27 Jan 2009 16:34:38 +0000 (17:34 +0100)]
Use spaces instead of tabs.

15 years agoPut getInstantiations in the State monad.
Matthijs Kooijman [Tue, 27 Jan 2009 16:32:56 +0000 (17:32 +0100)]
Put getInstantiations in the State monad.

15 years agoPut getArchitecture inside the State monad.
Matthijs Kooijman [Tue, 27 Jan 2009 15:01:57 +0000 (16:01 +0100)]
Put getArchitecture inside the State monad.

15 years agoMake the state monad calling code more pretty.
Matthijs Kooijman [Tue, 27 Jan 2009 14:50:44 +0000 (15:50 +0100)]
Make the state monad calling code more pretty.

15 years agoRun mkHWFunction and addFunc in a State monad.
Matthijs Kooijman [Tue, 27 Jan 2009 14:24:17 +0000 (15:24 +0100)]
Run mkHWFunction and addFunc in a State monad.

This uses a state consisting of a VHDLSession. The invocation of these
functions is a bit ugly now, that will be cleaned up next.

15 years agoDerive Show for the data types we define.
Matthijs Kooijman [Tue, 27 Jan 2009 13:36:17 +0000 (14:36 +0100)]
Derive Show for the data types we define.

15 years agoRemove the Args constructor, just use a list instead.
Matthijs Kooijman [Thu, 22 Jan 2009 19:34:54 +0000 (20:34 +0100)]
Remove the Args constructor, just use a list instead.

15 years agoLook up the port names in the session when generating an architecture.
Matthijs Kooijman [Thu, 22 Jan 2009 19:32:18 +0000 (20:32 +0100)]
Look up the port names in the session when generating an architecture.

15 years agoGenerate a HWFunction for the function that is being generated.
Matthijs Kooijman [Thu, 22 Jan 2009 19:28:34 +0000 (20:28 +0100)]
Generate a HWFunction for the function that is being generated.

15 years agoLookup input port names for instantiations in the session.
Matthijs Kooijman [Thu, 22 Jan 2009 16:40:04 +0000 (17:40 +0100)]
Lookup input port names for instantiations in the session.

This replaces the previously hardcoded portnames.

15 years agoMake getPortMapEntry accept a PortNameMap.
Matthijs Kooijman [Thu, 22 Jan 2009 16:37:14 +0000 (17:37 +0100)]
Make getPortMapEntry accept a PortNameMap.

15 years agoPass around a session variable.
Matthijs Kooijman [Thu, 22 Jan 2009 16:33:51 +0000 (17:33 +0100)]
Pass around a session variable.

This session variable stores a list of available functions and a number
for generating unique names. So far, the session is only used to lookup
output port names and is read only (ie, not returned from functions).

15 years agoUse ForSyDe.Backend.VHDL modules to generate VHDL.
Matthijs Kooijman [Thu, 22 Jan 2009 15:33:44 +0000 (16:33 +0100)]
Use ForSyDe.Backend.VHDL modules to generate VHDL.

The current code is still a bit hacky, but no longer contains hardcoded
VHDL and instead builds a VHDL AST which is then printed by modules from
ForSyDe.

Note that this uses internal ForSyDe modules. ForSyDe was modified to
expose these internal modules.

15 years agoRemove the entity generation code.
Matthijs Kooijman [Thu, 22 Jan 2009 13:55:47 +0000 (14:55 +0100)]
Remove the entity generation code.

15 years agoHandle tuple constructors in expressions.
Matthijs Kooijman [Wed, 21 Jan 2009 12:40:07 +0000 (13:40 +0100)]
Handle tuple constructors in expressions.

This enables a hardware model to have multiple output ports, using a tuple
type. The code is still a bit hacky and only works for two-tuples.

15 years agoLet the Adders module export everything.
Matthijs Kooijman [Wed, 21 Jan 2009 12:38:15 +0000 (13:38 +0100)]
Let the Adders module export everything.

15 years agoAdd a haskell model for a half adder.
Matthijs Kooijman [Wed, 21 Jan 2009 12:37:56 +0000 (13:37 +0100)]
Add a haskell model for a half adder.

15 years agoAdd an error message.
Matthijs Kooijman [Wed, 21 Jan 2009 10:52:37 +0000 (11:52 +0100)]
Add an error message.

15 years agoMap output ports as well as input ports.
Matthijs Kooijman [Wed, 21 Jan 2009 10:49:52 +0000 (11:49 +0100)]
Map output ports as well as input ports.

15 years agoGenerate input port names from the argument types.
Matthijs Kooijman [Wed, 21 Jan 2009 10:48:58 +0000 (11:48 +0100)]
Generate input port names from the argument types.

This replaces the hardcoded list of input port names which was used for
testing before.

15 years agoAdd .gitignore file.
Matthijs Kooijman [Mon, 19 Jan 2009 15:47:35 +0000 (16:47 +0100)]
Add .gitignore file.

15 years agoIntial import of some haskell programs.
Matthijs Kooijman [Mon, 19 Jan 2009 15:45:52 +0000 (16:45 +0100)]
Intial import of some haskell programs.

Contains the following files:
 * Adders.hs     - Some Haskell modelling of hardware adders.
 * Alu.hs        - A haskell model of an (extremely) simple cpu.
 * Bits.hs       - Stuff relating to a basic "Bit" datatype.
 * Inverter.hs   - A haskell model of an inverter.
 * Parser.hs     - A simple haskell parser using Language.Haskell libraries.
 * Shifter.hs    - A haskell model of an interactive xor-shifter.
 * Sim.hs        - Some utilities to run hardware models.
 * Translator.hs - A basic program that uses GHC to read Haskell code and
                   translates it into VHDL. This code is still very preliminary.