Add some comments.

diff --git a/Adders.hs b/Adders.hs
index c39857898abaa856a1206107c861115a4b08bfa1..f29927ceac3fd6e0804ade47ca5974ccae5ae333 100644 (file)
--- a/Adders.hs
+++ b/Adders.hs
@@ -10,18 +10,18 @@ show_add f = do print ("Sum:   " ++ (displaysigs s)); print ("Carry: " ++ (displ
     b = [Low, Low, Low, High]
     (s, c) = f (a, b)
 
--- Combinatoric no-carry adder
+-- Combinatoric stateless no-carry adder
 -- A -> B -> S
 no_carry_adder :: (Bit, Bit) -> Bit
 no_carry_adder (a, b) = a `hwxor` b
 
--- Combinatoric half adder
+-- Combinatoric stateless half adder
 -- A -> B -> (S, C)
 half_adder :: (Bit, Bit) -> (Bit, Bit)
 half_adder (a, b) = 
   ( a `hwxor` b, a `hwand` b )
 
--- Combinatoric (one-bit) full adder
+-- Combinatoric stateless full adder
 -- (A, B, C) -> (S, C)
 full_adder :: (Bit, Bit, Bit) -> (Bit, Bit)
 full_adder (a, b, cin) = (s, c)

diff --git a/Alu.hs b/Alu.hs
index 2495df25f0c80b885f4095012088e4f2b30f2623..59e5fd521a9ac856bc489eafbbb4d04cfc2cf2a8 100644 (file)
--- a/Alu.hs
+++ b/Alu.hs
@@ -16,8 +16,7 @@ program = [
 
 initial_state = ((Low, High), (), Low, Low)
 
---
---
+-- Register bank
 
 type RegAddr = Bit
 type RegisterBankState = (Bit, Bit)
@@ -40,6 +39,8 @@ register_bank (addr, High, d) s = -- Write
     r1' = if addr == High then d else r1
     s' = (r0', r1')
 
+-- ALU
+
 type AluState = ()
 type AluOp = Bit