Add a stateless circuit type.

diff --git a/Sim.hs b/Sim.hs
index c87f7605e727bed37e47898e9feb8346d36ea607..3848508c220b942412a3b9dd27b640abcb852e54 100644 (file)
--- a/Sim.hs
+++ b/Sim.hs
@@ -1,4 +1,4 @@
-module Sim (simulate, SCircuit, simulateIO) where
+module Sim (simulate, SCircuit, Circuit, simulateIO) where
 import Data.Typeable
 
 simulate f input s = do
@@ -13,6 +13,7 @@ simulate f input s = do
 
 -- A circuit with input of type a, state of type s and output of type b
 type SCircuit i s o = i -> s -> (s, o)
+type Circuit i o = i -> o
 
 run :: SCircuit i s o -> [i] -> s -> [(i, o, s)]
 run f (i:input) s =