From 8303bf12f3783a0603dcbeacd10ca3648bc0a2b1 Mon Sep 17 00:00:00 2001 From: Matthijs Kooijman Date: Fri, 30 Jan 2009 10:23:49 +0100 Subject: [PATCH] Add a stateless circuit type. --- Sim.hs | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Sim.hs b/Sim.hs index c87f760..3848508 100644 --- a/Sim.hs +++ b/Sim.hs @@ -1,4 +1,4 @@ -module Sim (simulate, SCircuit, simulateIO) where +module Sim (simulate, SCircuit, Circuit, simulateIO) where import Data.Typeable simulate f input s = do @@ -13,6 +13,7 @@ simulate f input s = do -- A circuit with input of type a, state of type s and output of type b type SCircuit i s o = i -> s -> (s, o) +type Circuit i o = i -> o run :: SCircuit i s o -> [i] -> s -> [(i, o, s)] run f (i:input) s = -- 2.30.2