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Move the DesignFile creation to VHDL.
[matthijs/master-project/cλash.git]
/
VHDL.hs
2009-02-17
Matthijs Kooijman
Move the DesignFile creation to VHDL.
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2009-02-17
Matthijs Kooijman
Add clk port on any stateful entity.
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2009-02-17
Matthijs Kooijman
Create state procs for state signals.
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2009-02-16
Matthijs Kooijman
Add port maps to component instantiations.
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2009-02-16
Matthijs Kooijman
Make application names unique.
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2009-02-16
Matthijs Kooijman
Let mkCompInsSm look up the actual VHDL entity id.
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2009-02-16
Matthijs Kooijman
Put mkCompInsSm in the VHDLState monad.
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2009-02-13
Matthijs Kooijman
Make modFuncs work with stateful functions.
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2009-02-13
Matthijs Kooijman
Generate dummy component instantiations for each archit...
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2009-02-13
Matthijs Kooijman
Use less general names as labels some fields.
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2009-02-13
Matthijs Kooijman
Generate a VHDL architecture for each function.
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2009-02-13
Matthijs Kooijman
Add port declarations to the VHDL entities.
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2009-02-13
Matthijs Kooijman
Put a TypeMark in a VHDLSignalmap.
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2009-02-13
Matthijs Kooijman
Rename fields of SignalInfo.
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2009-02-13
Matthijs Kooijman
Extract entities from the session and return them in...
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2009-02-13
Matthijs Kooijman
Generate VHDL entity declarations.
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2009-02-13
Matthijs Kooijman
Create an entity for each function.
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2009-02-13
Matthijs Kooijman
Remove NamedFlatFunction again.
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2009-02-11
Matthijs Kooijman
Move around a bunch of types.
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2009-02-11
Matthijs Kooijman
Greatly clean up Translator.
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