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Split off the VHDL type generating code.
[matthijs/master-project/cλash.git]
/
Adders.hs
2009-06-19
Christiaan Baaij
Adders.hs explicityly uses Prelude lists function....
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2009-06-19
Christiaan Baaij
Merge branch 'cλash' of git.stderr.nl/matthijs/projects...
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2009-06-19
Christiaan Baaij
Added function calls
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2009-06-19
Matthijs Kooijman
Add another higher order testcase, highordtest2.
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2009-06-19
Christiaan Baaij
Merge branch 'cλash' of git.stderr.nl/matthijs/projects...
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2009-06-18
Matthijs Kooijman
Add a higher order testcase.
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2009-06-15
Matthijs Kooijman
Generate VHDL from Core instead of flat functions.
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2009-05-25
Matthijs Kooijman
Update the hardware models a bit.
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2009-03-04
Matthijs Kooijman
Add some hardware models using vectors (FSVec).
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2009-03-03
Matthijs Kooijman
Never inline the half_adder function.
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2009-02-27
Matthijs Kooijman
Add a two-port mux hardware model.
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2009-02-18
Matthijs Kooijman
Add a simple four-bit shift register model.
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2009-02-11
Matthijs Kooijman
Give stateless a type signature.
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2009-02-02
Matthijs Kooijman
Add a D-Flip flop hardware model.
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2009-02-02
Matthijs Kooijman
Add a full_adder version with stateful interface.
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2009-01-30
Matthijs Kooijman
Give Adders a mainIO to to interactive simulation.
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2009-01-30
Matthijs Kooijman
Implement full_adder in terms of half_adder.
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2009-01-29
Matthijs Kooijman
Make full_adder simpler.
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2009-01-29
Matthijs Kooijman
Add a duplication hardware model.
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2009-01-29
Matthijs Kooijman
Add a double invertor model.
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2009-01-29
Matthijs Kooijman
Add an invertor hardware model.
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2009-01-29
Matthijs Kooijman
Add a trivial "wire" hardware model.
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2009-01-29
Matthijs Kooijman
Add some comments.
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2009-01-21
Matthijs Kooijman
Let the Adders module export everything.
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2009-01-21
Matthijs Kooijman
Add a haskell model for a half adder.
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2009-01-19
Matthijs Kooijman
Intial import of some haskell programs.
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