Generate VHDL from Core instead of flat functions.

Generate VHDL from Core instead of flat functions.

This bypasses all of the Flatten functionality for now and generates VHDL
directly. The generation only works on very simple Core programs, that are
already in normal form. An example of such a program is the inv function
in Adders.hs.

For now, all state generation is broken again. Support for ValueMaps has
mostly been removed, since in the future tuples will be translated to
records in VHDL instead of being flattened.