Generate VHDL from Core instead of flat functions.

[matthijs/master-project/cλash.git] / Adders.hs

diff --git a/Adders.hs b/Adders.hs
index e6676e94888f3ce0bec9c9a489672da8288200e0..249bb3a4ef983a84f7f3074f131934688b2974b3 100644 (file)
--- a/Adders.hs
+++ b/Adders.hs
@@ -53,7 +53,7 @@ instance Inv (BitVec D0) where
 -}
 -- Not really an adder either, but a slightly more complex example
 inv :: Bit -> Bit
-inv a = hwnot a
+inv a = let r = hwnot a in r
 
 -- Not really an adder either, but a slightly more complex example
 invinv :: Bit -> Bit