Generate VHDL from Core instead of flat functions.

[matthijs/master-project/cλash.git] / VHDLTypes.hs

diff --git a/VHDLTypes.hs b/VHDLTypes.hs
index 33010822b9ace9ec74e0002e0ba015fd2643254b..784b09706e6a6742a4fb504640983e8973349225 100644 (file)
--- a/VHDLTypes.hs
+++ b/VHDLTypes.hs
@@ -12,6 +12,7 @@ import qualified Data.Accessor.Template
 
 -- GHC API imports
 import qualified Type
+import qualified CoreSyn
 
 -- ForSyDe imports
 import qualified ForSyDe.Backend.VHDL.AST as AST
@@ -30,8 +31,8 @@ type VHDLSignalMap = HsValueMap VHDLSignalMapElement
 -- ports.
 data Entity = Entity { 
   ent_id     :: AST.VHDLId,           -- The id of the entity
-  ent_args   :: [VHDLSignalMap],      -- A mapping of each function argument to port names
-  ent_res    :: VHDLSignalMap         -- A mapping of the function result to port names
+  ent_args   :: [VHDLSignalMapElement],      -- A mapping of each function argument to port names
+  ent_res    :: VHDLSignalMapElement         -- A mapping of the function result to port names
 } deriving (Show);
 
 -- A orderable equivalent of CoreSyn's Type for use as a map key
@@ -45,7 +46,7 @@ instance Ord OrdType where
 type TypeMap = Map.Map OrdType (AST.VHDLId, AST.TypeDec)
 
 -- A map of a Haskell function to a hardware signature
-type SignatureMap = Map.Map HsFunction Entity
+type SignatureMap = Map.Map String Entity
 
 data VHDLSession = VHDLSession {
   -- | A map of Core type -> VHDL Type