Fix typos

[matthijs/master-project/haskell-symposium-talk.git] / reducer.lhs

diff --git a/reducer.lhs b/reducer.lhs
index 21baeeb9db140eb52b071981ba1403677a7b8313..061f9dbc85da8df260ad574aae2970c988862cab 100644 (file)
--- a/reducer.lhs
+++ b/reducer.lhs
@@ -10,7 +10,7 @@
 \column{0.5\textwidth}
 \begin{itemize}
   \item We implemented a reduction circuit in \clash{}\pause
-  \item Simulated first Haskell. VHDL simulation results match\pause
+  \item Simulated in Haskell. VHDL simulation results match\pause
   \item Synthesis completes without errors or warnings\pause
   \item Around half speed of handcoded and optimized VHDL
 \end{itemize}