X-Git-Url: https://git.stderr.nl/gitweb?p=matthijs%2Fmaster-project%2Fhaskell-symposium-talk.git;a=blobdiff_plain;f=reducer.lhs;fp=reducer.lhs;h=061f9dbc85da8df260ad574aae2970c988862cab;hp=21baeeb9db140eb52b071981ba1403677a7b8313;hb=8dbb9f84b45c91f448bdb71067b450014c2d4b64;hpb=b4b0e8a2e09609f70bc5ed0fb69a8d966e4a6813

diff --git a/reducer.lhs b/reducer.lhs
index 21baeeb..061f9db 100644
--- a/reducer.lhs
+++ b/reducer.lhs
@@ -10,7 +10,7 @@
 \column{0.5\textwidth}
 \begin{itemize}
   \item We implemented a reduction circuit in \clash{}\pause
-  \item Simulated first Haskell. VHDL simulation results match\pause
+  \item Simulated in Haskell. VHDL simulation results match\pause
   \item Synthesis completes without errors or warnings\pause
   \item Around half speed of handcoded and optimized VHDL
 \end{itemize}