Add reference to Haskell and Verilog. Add something about state to introduction
[matthijs/master-project/dsd-paper.git] / .gitignore
index 39ce533756e39e4d34cbc45961da4b2def36cc69..2c4bbc94626d1e4915d21cbd204a65c50c03cfe2 100644 (file)
@@ -6,3 +6,4 @@
 *.pdf
 *.bak
 .latexmkrc
+c╬╗ash.tex