Process most of jan's comments

[matthijs/master-project/dsd-paper.git] / cλash.lhs

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\def\acro#1{{\small{#1}}}
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\def\VHDL{\acro{VHDL}}
\def\GHC{\acro{GHC}}
\def\CLaSH{{\small{C}}$\lambda$a{\small{SH}}}
\def\CLaSHtiny{{\scriptsize{C}}$\lambda$a{\scriptsize{SH}}}

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%include polycode.fmt
%include clash.fmt

\begin{document}
%
% paper title
% can use linebreaks \\ within to get better formatting as desired
\title{C$\lambda$aSH: Structural Descriptions \\ of Synchronous Hardware using Haskell}


% author names and affiliations
% use a multiple column layout for up to three different
% affiliations
\author{\IEEEauthorblockN{Christiaan P.R. Baaij, Matthijs Kooijman, Jan Kuper, Marco E.T. Gerards}%, Bert Molenkamp, Sabih H. Gerez}
\IEEEauthorblockA{%Computer Architecture for Embedded Systems (CAES)\\ 
Department of EEMCS, University of Twente\\
P.O. Box 217, 7500 AE, Enschede, The Netherlands\\
c.p.r.baaij@@utwente.nl, matthijs@@stdin.nl, j.kuper@@utwente.nl}
\thanks{Supported through the FP7 project: S(o)OS (248465)}
}
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% Springfield, USA\\
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%Homer Simpson\IEEEauthorrefmark{2},
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%Montgomery Scott\IEEEauthorrefmark{3} and
%Eldon Tyrell\IEEEauthorrefmark{4}}
%\IEEEauthorblockA{\IEEEauthorrefmark{1}School of Electrical and Computer Engineering\\
%Georgia Institute of Technology,
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%\IEEEauthorblockA{\IEEEauthorrefmark{2}Twentieth Century Fox, Springfield, USA\\
%Email: homer@thesimpsons.com}
%\IEEEauthorblockA{\IEEEauthorrefmark{3}Starfleet Academy, San Francisco, California 96678-2391\\
%Telephone: (800) 555--1212, Fax: (888) 555--1212}
%\IEEEauthorblockA{\IEEEauthorrefmark{4}Tyrell Inc., 123 Replicant Street, Los Angeles, California 90210--4321}}




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% make the title area
\maketitle

\begin{abstract}
%\boldmath
\CLaSH\ is a functional hardware description language that borrows both its 
syntax and semantics from the functional programming language Haskell. Due to 
the abstraction and generality offered by polymorphism and higher-order 
functions, a circuit designer can describe circuits in a more natural way than 
he could in the traditional hardware description languages.

Circuit descriptions can be translated to synthesizable VHDL using the 
prototype \CLaSH\ compiler. As the circuit descriptions, simulation code, and 
test input are also valid Haskell, complete simulations can be compiled to an 
executable binary by a Haskell compiler allowing high-speed simulation and 
analysis.

Stateful descriptions are supported by explicitly making the current state an 
argument of the function, and the updated state part of the result. In this 
sense, the descriptions made in \CLaSH\ are the combinational parts of a mealy 
machine.
\end{abstract}
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\section{Introduction}
Hardware description languages have allowed the productivity of hardware 
engineers to keep pace with the development of chip technology. Standard 
Hardware description languages, like \VHDL~\cite{VHDL2008} and 
Verilog~\cite{Verilog}, allowed an engineer to describe circuits using a 
programming language. These standard languages are very good at describing 
detailed hardware properties such as timing behavior, but are generally 
cumbersome in expressing higher-level abstractions. In an attempt to raise the 
abstraction level of the descriptions, a great number of approaches based on 
functional languages has been proposed \cite{T-Ruby,Hydra,HML2,Hawk1,Lava,
ForSyDe1,Wired,reFLect}. The idea of using functional languages for hardware 
descriptions started in the early 1980s \cite{Cardelli1981, muFP,DAISY,FHDL}, 
a time which also saw the birth of the currently popular hardware description 
languages such as \VHDL. Functional languages are especially suited to
describe hardware because combinational circuits can be directly modeled
as mathematical functions. Furthermore, functional languages are very good at
describing and composing mathematical functions.

In an attempt to decrease the amount of work involved in creating all the 
required tooling, such as parsers and type-checkers, many functional
hardware description languages \cite{Hydra,Hawk1,Lava,ForSyDe1,Wired}
are embedded as a domain specific language inside the functional
language Haskell \cite{Haskell}. This means that a developer is given a
library of Haskell functions and types that together form the language
primitives of the domain specific language. The primitive functions used
to describe a circuit do not actually process any signals, but instead
compose a large domain-specific datatype (which is usually hidden from
the designer).  This datatype is then further processed by an embedded
circuit compiler.  This circuit compiler actually runs in the same
environment as the description; as a result compile-time and run-time
become hard to define, as the embedded circuit compiler is usually
compiled by the same Haskell compiler as the circuit description itself.

The approach taken in this research is not to make another domain specific 
language embedded in Haskell, but to use (a subset of) the Haskell language 
\emph{itself} for the purpose of describing hardware. By taking this approach, 
we can capture certain language constructs, such as Haskell's choice elements 
(if-expressions, case-expressions, pattern matching, etc.), which are not 
available in the functional hardware description languages that are embedded 
in Haskell as a domain specific language. As far as the authors know, such 
extensive support for choice-elements is new in the domain of functional 
hardware description languages. As the hardware descriptions are plain Haskell 
functions, these descriptions can be compiled to an executable binary
for simulation using an optimizing Haskell compiler such as the Glasgow
Haskell Compiler (\GHC)~\cite{ghc}.

Where descriptions in a conventional hardware description language have an 
explicit clock for the purposes state and synchronicity, in the research 
presented in this paper the clock is implied. A developer describes the 
behavior of the hardware between clock cycles. Many functional hardware 
description model signals as a stream of all values over time; state is then 
modeled as a delay on this stream of values. The approach taken in this 
research is to make the current state of a circuit part of the input of the 
function and the updated state part of the output. The current abstraction of 
state and time limits the descriptions to synchronous hardware, there however 
is room within the language to eventually add a different abstraction 
mechanism that will allow for the modeling of asynchronous systems.

Like the standard hardware description languages, descriptions made in a 
functional hardware description language must eventually be converted into a 
netlist. This research also features a prototype translator, which has the 
same name as the language: \CLaSH\footnote{\CLaSHtiny: \acrotiny{CAES} 
Language for Synchronous Hardware} (pronounced: clash). This compiler converts 
the Haskell code to equivalently behaving synthesizable \VHDL\ code, ready to 
be converted to an actual netlist format by an (optimizing) \VHDL\ synthesis 
tool.

Besides trivial circuits such as variants of both the \acro{FIR} filter and 
the simple \acro{CPU} shown in \Cref{sec:usecases}, the \CLaSH\ compiler has 
also been shown to work for non-trivial descriptions. \CLaSH\ has been able to 
successfully translate the functional description of a streaming reduction 
circuit~\cite{reductioncircuit} for floating point numbers.

\section{Hardware description in Haskell}

  \subsection{Function application}
    Two basic syntactic elements of a functional program are functions
    and function application. These have a single obvious translation to a 
    netlist format: 
    \begin{inparaenum}
      \item every function is translated to a component, 
      \item every function argument is translated to an input port,
      \item the result value of a function is translated to an output port, 
            and
      \item function applications are translated to component instantiations.
    \end{inparaenum} 
    The result value can have a composite type (such as a tuple), so having 
    just a single result value does not pose any limitation. The actual 
    arguments of a function application are assigned to signals, which are 
    then mapped to the corresponding input ports of the component. The output 
    port of the function is also mapped to a signal, which is used as the 
    result of the application itself. Since every top level function generates 
    its own component, the hierarchy of function calls is reflected in the 
    final netlist, creating a hierarchical description of the hardware. 
    % The separation in different components makes it easier for a developer 
    % to understand and possibly hand-optimize the resulting \VHDL\ output of 
    % the \CLaSH\ compiler.

    The short example demonstrated below gives an indication of the level of 
    conciseness that can be achieved with functional hardware description 
    languages when compared with the more traditional hardware description 
    languages. The example is a combinational multiply-accumulate circuit that 
    works for \emph{any} word length (this type of polymorphism will be 
    further elaborated in \Cref{sec:polymorhpism}). The corresponding netlist 
    is depicted in \Cref{img:mac-comb}.
    
    \begin{code}
    mac a b c = add (mul a b) c
    \end{code}
    
    \begin{figure}
    \centerline{\includegraphics{mac.svg}}
    \caption{Combinatorial Multiply-Accumulate}
    \label{img:mac-comb}
    \end{figure}
    
    The use of a composite result value is demonstrated in the next example, 
    where the multiply-accumulate circuit not only returns the accumulation 
    result, but also the intermediate multiplication result. Its corresponding
    netlist can be see in \Cref{img:mac-comb-composite}.
    
    \begin{code}
    mac a b c = (z, add z c)
      where
        z = mul a b
    \end{code}
    
    \begin{figure}
    \centerline{\includegraphics{mac-nocurry.svg}}
    \caption{Combinatorial Multiply-Accumulate (composite output)}
    \label{img:mac-comb-composite}
    \end{figure}

  \subsection{Choice}
    In Haskell, choice can be achieved by a large set of syntactic elements, 
    consisting of: \hs{case} expressions, \hs{if-then-else} expressions, 
    pattern matching, and guards. The most general of these are the \hs{case} 
    expressions (\hs{if} expressions can be very directly translated to 
    \hs{case} expressions). A \hs{case} expression is translated to a 
    multiplexer, where the control value is fed into a number of
    comparators and their output is used to compose the selection port
    of the multiplexer. The result of each alternative is linked to the
    corresponding input port on the multiplexer.
    % A \hs{case} expression can in turn simply be translated to a conditional 
    % assignment in \VHDL, where the conditions use equality comparisons 
    % against the constructors in the \hs{case} expressions. 
    We can see two versions of a contrived example below, the first 
    using a \hs{case} expression and the other using an \hs{if-then-else} 
    expression. Both examples sums two values when they are 
    equal or non-equal (depending on the given predicate, the \hs{pred} 
    variable) and returns 0 otherwise. The \hs{pred} variable has the 
    following, user-defined, enumeration datatype:
    
    \begin{code}
    data Pred = Equal | NotEqual
    \end{code}

    The naive netlist corresponding to both versions of the example is 
    depicted in \Cref{img:choice}. Note that the \hs{pred} variable is only
    compared to the \hs{Equal} value, as an inequality immediately implies 
    that the \hs{pred} variable has a \hs{NotEqual} value.

    \begin{code}    
    sumif pred a b = case pred of
      Equal -> case a == b of
        True      -> a + b
        False     -> 0
      NotEqual  -> case a != b of
        True      -> a + b
        False     -> 0
    \end{code}

    \begin{code}
    sumif pred a b = 
      if pred == Equal then 
        if a == b then a + b else 0
      else 
        if a != b then a + b else 0
    \end{code}

    \begin{figure}
    \centerline{\includegraphics{choice-case.svg}}
    \caption{Choice - sumif}
    \label{img:choice}
    \end{figure}

    A user-friendly and also very powerful form of choice that is not found in 
    the traditional hardware description languages is pattern matching. A 
    function can be defined in multiple clauses, where each clause corresponds 
    to a pattern. When an argument matches a pattern, the corresponding clause 
    will be used. Expressions can also contain guards, where the expression is 
    only executed if the guard evaluates to true, and continues with the next 
    clause if the guard evaluates to false. Like \hs{if-then-else} 
    expressions, pattern matching and guards have a (straightforward) 
    translation to \hs{case} expressions and can as such be mapped to 
    multiplexers. A third version of the earlier example, using both pattern 
    matching and guards, can be seen below. The guard is the expression that 
    follows the vertical bar (\hs{|}) and precedes the assignment operator 
    (\hs{=}). The \hs{otherwise} guards always evaluate to \hs{true}.
    
    The version using pattern matching and guards corresponds to the same 
    naive netlist representation (\Cref{img:choice}) as the earlier two 
    versions of the example.
    
    \begin{code}
    sumif Equal     a b   | a == b      = a + b
                          | otherwise   = 0
    sumif NotEqual  a b   | a != b      = a + b
                          | otherwise   = 0
    \end{code}

    % \begin{figure}
    % \centerline{\includegraphics{choice-ifthenelse}}
    % \caption{Choice - \emph{if-then-else}}
    % \label{img:choice}
    % \end{figure}

  \subsection{Types}
    Haskell is a statically-typed language, meaning that the type of a 
    variable or function is determined at compile-time. Not all of Haskell's 
    typing constructs have a clear translation to hardware, this section will 
    therefore only deal with the types that do have a clear correspondence 
    to hardware. The translatable types are divided into two categories: 
    \emph{built-in} types and \emph{user-defined} types. Built-in types are 
    those types for which a fixed translation is defined within the \CLaSH\ 
    compiler. The \CLaSH\ compiler has generic translation rules to
    translated the user-defined types described below.

    The \CLaSH\ compiler is able to infer unspecified types,
    meaning that a developer does not have to annotate every function with a 
    type signature (even if it is good practice to do so).
  
    % Translation of two most basic functional concepts has been
    % discussed: function application and choice. Before looking further
    % into less obvious concepts like higher-order expressions and
    % polymorphism, the possible types that can be used in hardware
    % descriptions will be discussed.
    % 
    % Some way is needed to translate every value used to its hardware
    % equivalents. In particular, this means a hardware equivalent for
    % every \emph{type} used in a hardware description is needed.
    % 
    % The following types are \emph{built-in}, meaning that their hardware
    % translation is fixed into the \CLaSH\ compiler. A designer can also
    % define his own types, which will be translated into hardware types
    % using translation rules that are discussed later on.

  \subsubsection{Built-in types}
    The following types have fixed translations defined within the \CLaSH\
    compiler:
    \begin{xlist}
      \item[\bf{Bit}]
        the most basic type available. It can have two values:
        \hs{Low} or \hs{High}. 
        % It is mapped directly onto the \texttt{std\_logic} \VHDL\ type. 
      \item[\bf{Bool}]
        this is a basic logic type. It can have two values: \hs{True}
        or \hs{False}. 
        % It is translated to \texttt{std\_logic} exactly like the \hs{Bit} 
        % type (where a value of \hs{True} corresponds to a value of 
        % \hs{High}). 
        Supporting the Bool type is required in order to support the
        \hs{if-then-else} expression, which requires a \hs{Bool} value for 
        the condition.
      \item[\bf{SizedWord}, \bf{SizedInt}]
        these are types to represent integers. A \hs{SizedWord} is unsigned,
        while a \hs{SizedInt} is signed. Both are parametrizable in their 
        size. 
        % , so you can define an unsigned word of 32 bits wide as follows:

        % \begin{code}
        % type Word32 = SizedWord D32
        % \end{code}

        % Here, a type synonym \hs{Word32} is defined that is equal to the
        % \hs{SizedWord} type constructor applied to the type \hs{D32}. 
        % \hs{D32} is the \emph{type level representation} of the decimal 
        % number 32, making the \hs{Word32} type a 32-bit unsigned word. These 
        % types are translated to the \VHDL\ \texttt{unsigned} and 
        % \texttt{signed} respectively.
      \item[\bf{Vector}]
        this is a vector type that can contain elements of any other type and
        has a fixed length. The \hs{Vector} type constructor takes two type 
        arguments: the length of the vector and the type of the elements 
        contained in it. The short-hand notation used for the vector type in  
        the rest of paper is: \hs{[a|n]}, here \hs{a} is the element 
        type, and \hs{n} is the length of the vector. Note that this is
        a notation used in this paper only, vectors are slightly more
        verbose in real \CLaSH\ descriptions.
        % The state type of an 8 element register bank would then for example 
        % be:

        % \begin{code}
        % type RegisterState = Vector D8 Word32
        % \end{code}

        % Here, a type synonym \hs{RegisterState} is defined that is equal to
        % the \hs{Vector} type constructor applied to the types \hs{D8} (The 
        % type level representation of the decimal number 8) and \hs{Word32} 
        % (The 32 bit word type as defined above). In other words, the 
        % \hs{RegisterState} type is a vector of 8 32-bit words. A fixed size 
        % vector is translated to a \VHDL\ array type.
      \item[\bf{Index}]
        this is another type to describe integers, but unlike the previous
        two it has no specific bit-width, but an upper bound. This means that
        its range is not limited to powers of two, but can be any number.
        An \hs{Index} only has an upper bound, its lower bound is
        implicitly zero. The main purpose of the \hs{Index} type is to be 
        used as an index to a \hs{Vector}.

        % \comment{TODO: Perhaps remove this example?} To define an index for 
        % the 8 element vector above, we would do:

        % \begin{code}
        % type RegisterIndex = RangedWord D7
        % \end{code}

        % Here, a type synonym \hs{RegisterIndex} is defined that is equal to
        % the \hs{RangedWord} type constructor applied to the type \hs{D7}. In
        % other words, this defines an unsigned word with values from
        % 0 to 7 (inclusive). This word can be be used to index the
        % 8 element vector \hs{RegisterState} above. This type is translated 
        % to the \texttt{unsigned} \VHDL type.
    \end{xlist}

  \subsubsection{User-defined types}
    There are three ways to define new types in Haskell: algebraic
    data-types with the \hs{data} keyword, type synonyms with the \hs{type}
    keyword and datatype renaming constructs with the \hs{newtype} keyword. 
    \GHC\ offers a few more advanced ways to introduce types (type families,
    existential typing, {\acro{GADT}}s, etc.) which are not standard Haskell. 
    As it is currently unclear how these advanced type constructs correspond 
    to hardware, they are for now unsupported by the \CLaSH\ compiler.

    Only an algebraic datatype declaration actually introduces a
    completely new type. Type synonyms and type renaming only define new 
    names for existing types, where synonyms are completely interchangeable 
    and type renaming requires explicit conversions. Therefore, these do not 
    need any particular translation, a synonym or renamed type will just use 
    the same representation as the original type. 
    
    For algebraic types, we can make the following distinctions:
    \begin{xlist}
      \item[\bf{Single constructor}]
        Algebraic datatypes with a single constructor with one or more
        fields, are essentially a way to pack a few values together in a
        record-like structure. Haskell's built-in tuple types are also defined 
        as single constructor algebraic types (but with a bit of
        syntactic sugar). An example of a single constructor type is the
        following pair of integers:
        \begin{code}
        data IntPair = IntPair Int Int
        \end{code}
        % These types are translated to \VHDL\ record types, with one field 
        % for every field in the constructor.
      \item[\bf{No fields}]
        Algebraic datatypes with multiple constructors, but without any
        fields are essentially a way to get an enumeration-like type
        containing alternatives. Note that Haskell's \hs{Bool} type is also 
        defined as an enumeration type, but that there is a fixed translation 
        for that type within the \CLaSH\ compiler. An example of such an 
        enumeration type is the type that represents the colors in a traffic 
        light:
        \begin{code}
        data TrafficLight = Red | Orange | Green
        \end{code}
        % These types are translated to \VHDL\ enumerations, with one 
        % value for each constructor. This allows references to these 
        % constructors to be translated to the corresponding enumeration 
        % value.
      \item[\bf{Multiple constructors with fields}]
        Algebraic datatypes with multiple constructors, where at least
        one of these constructors has one or more fields are currently not 
        supported.
    \end{xlist}

  \subsection{Polymorphism}\label{sec:polymorhpism}
    A powerful feature of most (functional) programming languages is 
    polymorphism, it allows a function to handle values of different data 
    types in a uniform way. Haskell supports \emph{parametric 
    polymorphism}~\cite{polymorphism}, meaning functions can be written 
    without mention of any specific type and can be used transparently with 
    any number of new types.

    As an example of a parametric polymorphic function, consider the type of 
    the following \hs{append} function, which appends an element to a
    vector:\footnote{The \hs{::} operator is used to annotate a function
    with its type.}
    
    \begin{code}
    append :: [a|n] -> a -> [a|n + 1]
    \end{code}

    This type is parameterized by \hs{a}, which can contain any type at
    all. This means that \hs{append} can append an element to a vector,
    regardless of the type of the elements in the list (as long as the type of 
    the value to be added is of the same type as the values in the vector). 
    This kind of polymorphism is extremely useful in hardware designs to make 
    operations work on a vector without knowing exactly what elements are 
    inside, routing signals without knowing exactly what kinds of signals 
    these are, or working with a vector without knowing exactly how long it 
    is. Polymorphism also plays an important role in most higher order 
    functions, as we will see in the next section.

    Another type of polymorphism is \emph{ad-hoc 
    polymorphism}~\cite{polymorphism}, which refers to polymorphic 
    functions which can be applied to arguments of different types, but which 
    behave differently depending on the type of the argument to which they are 
    applied. In Haskell, ad-hoc polymorphism is achieved through the use of 
    type classes, where a class definition provides the general interface of a 
    function, and class instances define the functionality for the specific 
    types. An example of such a type class is the \hs{Num} class, which 
    contains all of Haskell's numerical operations. A designer can make use 
    of this ad-hoc polymorphism by adding a constraint to a parametrically 
    polymorphic type variable. Such a constraint indicates that the type 
    variable can only be instantiated to a type whose members supports the 
    overloaded functions associated with the type class. 
    
    As an example we will take a look at type signature of the function 
    \hs{sum}, which sums the values in a vector:
    \begin{code}
    sum :: Num a => [a|n] -> a
    \end{code}

    This type is again parameterized by \hs{a}, but it can only contain
    types that are \emph{instances} of the \emph{type class} \hs{Num}, so that  
    we know that the addition (+) operator is defined for that type. 
    \CLaSH's built-in numerical types are also instances of the \hs{Num}
    class, so we can use the addition operator (and thus the \hs{sum}
    function) with \hs{SizedWords} as well as with \hs{SizedInts}.

    In \CLaSH, parametric polymorphism is completely supported. Any function 
    defined can have any number of unconstrained type parameters. The \CLaSH\ 
    compiler will infer the type of every such argument depending on how the 
    function is applied. There is however one constraint: the top level 
    function that is being translated can not have any polymorphic arguments. 
    The arguments can not be polymorphic as the function is never applied and 
    consequently there is no way to determine the actual types for the type 
    parameters.

    \CLaSH\ does \emph{currently} not support\emph{ user-defined} type 
    classes, but does use some of the standard Haskell type classes for its 
    built-in function, such as: \hs{Num} for numerical operations, \hs{Eq} for 
    the equality operators, and \hs{Ord} for the comparison/order operators.

  \subsection{Higher-order functions \& values}
    Another powerful abstraction mechanism in functional languages, is
    the concept of \emph{higher-order functions}, or \emph{functions as
    a first class value}. This allows a function to be treated as a
    value and be passed around, even as the argument of another
    function. The following example should clarify this concept:
    
%format not = "\mathit{not}"
    \begin{code}
    negateVector xs = map not xs
    \end{code}

    The code above defines the \hs{negateVector} function, which takes a 
    vector of booleans, \hs{xs}, and returns a vector where all the values are 
    negated. It achieves this by calling the \hs{map} function, and passing it 
    \emph{another function}, boolean negation, and the vector of booleans, 
    \hs{xs}. The \hs{map} function applies the negation function to all the 
    elements in the vector.

    The \hs{map} function is called a higher-order function, since it takes 
    another function as an argument. Also note that \hs{map} is again a 
    parametric polymorphic function: it does not pose any constraints on the 
    type of the input vector, other than that its elements must have the same 
    type as the first argument of the function passed to \hs{map}. The element 
    type of the resulting vector is equal to the return type of the function 
    passed, which need not necessarily be the same as the element type of the 
    input vector. All of these characteristics  can readily be inferred from 
    the type signature belonging to \hs{map}:

    \begin{code}
    map :: (a -> b) -> [a|n] -> [b|n]
    \end{code}

    So far, only functions have been used as higher-order values. In
    Haskell, there are two more ways to obtain a function-typed value:
    partial application and lambda abstraction. Partial application
    means that a function that takes multiple arguments can be applied
    to a single argument, and the result will again be a function (but
    that takes one argument less). As an example, consider the following
    expression, that adds one to every element of a vector:

    \begin{code}
    map (add 1) xs
    \end{code}

    Here, the expression \hs{(add 1)} is the partial application of the
    addition function to the value \hs{1}, which is again a function that
    adds one to its (next) argument. A lambda expression allows one to 
    introduce an anonymous function in any expression. Consider the following 
    expression, which again adds one to every element of a vector:

    \begin{code}
    map (\x -> x + 1) xs
    \end{code}

    Finally, not only built-in functions can have higher order
    arguments, but any function defined in \CLaSH can have function
    arguments. This allows the hardware designer to use a powerful
    abstraction mechanism in his designs and have an optimal amount of
    code reuse. The only exception is again the top-level function: if a 
    function-typed argument is not applied with an actual function, no 
    hardware can be generated.    

    % \comment{TODO: Describe ALU example (no code)}

  \subsection{State}
    A very important concept in hardware is the concept of state. In a 
    stateful design, the outputs depend on the history of the inputs, or the 
    state. State is usually stored in registers, which retain their value 
    during a clock cycle. As we want to describe more than simple 
    combinational designs, \CLaSH\ needs an abstraction mechanism for state.

    An important property in Haskell, and in most other functional languages, 
    is \emph{purity}. A function is said to be \emph{pure} if it satisfies two
    conditions:
    \begin{inparaenum}
      \item given the same arguments twice, it should return the same value in 
      both cases, and
      \item that the function has no observable side-effects.
    \end{inparaenum}
    % This purity property is important for functional languages, since it 
    % enables all kinds of mathematical reasoning that could not be guaranteed 
    % correct for impure functions. 
    Pure functions are as such a perfect match for combinational circuits, 
    where the output solely depends on the inputs. When a circuit has state 
    however, it can no longer be simply described by a pure function. 
    % Simply removing the purity property is not a valid option, as the 
    % language would then lose many of it mathematical properties. 
    In \CLaSH\ we deal with the concept of state in pure functions by making 
    current value of the state an additional argument of the function and the 
    updated state part of result. In this sense the descriptions made in 
    \CLaSH\ are the combinational parts of a mealy machine.
    
    A simple example is adding an accumulator register to the earlier 
    multiply-accumulate circuit, of which the resulting netlist can be seen in 
    \Cref{img:mac-state}:
    
    \begin{code}
    macS (State c) a b = (State c', c')
      where
        c' = mac a b c
    \end{code}
    
    \begin{figure}
    \centerline{\includegraphics{mac-state.svg}}
    \caption{Stateful Multiply-Accumulate}
    \label{img:mac-state}
    \end{figure}
    
    Note that the \hs{macS} function returns bot the new state and the value
    of the output port. The \hs{State} keyword indicates which arguments are 
    part of the current state, and what part of the output is part of the 
    updated state. This aspect will also be reflected in the type signature of 
    the function. Abstracting the state of a circuit in this way makes it very 
    explicit: which variables are part of the state is completely determined 
    by the type signature. This approach to state is well suited to be used in 
    combination with the existing code and language features, such as all the 
    choice elements, as state values are just normal values. We can simulate 
    stateful descriptions using the recursive \hs{run} function:
    
    \begin{code}
    run f s (i : inps) = o : (run f s' inps)
      where
        (s', o) = f s i
    \end{code}
    
    The \hs{(:)} operator is the list concatenation operator, where the 
    left-hand side is the head of a list and the right-hand side is the 
    remainder of the list. The \hs{run} function applies the function the 
    developer wants to simulate, \hs{f}, to the current state, \hs{s}, and the 
    first input value, \hs{i}. The result is the first output value, \hs{o}, 
    and the updated state \hs{s'}. The next iteration of the \hs{run} function 
    is then called with the updated state, \hs{s'}, and the rest of the 
    inputs, \hs{inps}. For the time being, and in the context of this paper, 
    It is assumed that there is one input per clock cycle.
    Also note how the order of the input, output, and state in the \hs{run} 
    function corresponds with the order of the input, output and state of the 
    \hs{macS} function described earlier.
    
    As the \hs{run} function, the hardware description, and the test 
    inputs are also valid Haskell, the complete simulation can be compiled to 
    an executable binary by an optimizing Haskell compiler, or executed in an 
    Haskell interpreter. Both simulation paths are much faster than first 
    translating the description to \VHDL\ and then running a \VHDL\ 
    simulation.
    
\section{The \CLaSH\ compiler}
An important aspect in this research is the creation of the prototype 
compiler, which allows us to translate descriptions made in the \CLaSH\ 
language as described in the previous section to synthesizable \VHDL, allowing 
a designer to actually run a \CLaSH\ design on an \acro{FPGA}.

The Glasgow Haskell Compiler (\GHC) is an open-source Haskell compiler that 
also provides a high level API to most of its internals. The availability of 
this high-level API obviated the need to design many of the tedious parts of 
the prototype compiler, such as the parser, semantic checker, and especially 
the type-checker. These parts together form the front-end of the prototype compiler pipeline, as seen in \Cref{img:compilerpipeline}.

\begin{figure}
\centerline{\includegraphics{compilerpipeline.svg}}
\caption{\CLaSHtiny\ compiler pipeline}
\label{img:compilerpipeline}
\end{figure}

The output of the \GHC\ front-end consists of the translation of the original Haskell description in \emph{Core}~\cite{Sulzmann2007}, which is a smaller, typed, functional language. This \emph{Core} language is relatively easy to process compared to the larger Haskell language. A description in \emph{Core} can still contain elements which have no direct translation to hardware, such as polymorphic types and function-valued arguments. Such a description needs to be transformed to a \emph{normal form}, which only contains elements that have a direct translation. The second stage of the compiler, the \emph{normalization} phase, exhaustively applies a set of \emph{meaning-preserving} transformations on the \emph{Core} description until this description is in a \emph{normal form}. This set of transformations includes transformations typically found in reduction systems and lambda calculus~\cite{lambdacalculus}, such as $\beta$-reduction and $\eta$-expansion. It also includes self-defined transformations that are responsible for the reduction of higher-order functions to `regular' first-order functions.

The final step in the compiler pipeline is the translation to a \VHDL\ 
\emph{netlist}, which is a straightforward process due to resemblance of a 
normalized description and a set of concurrent signal assignments. We call the 
end-product of the \CLaSH\ compiler a \VHDL\ \emph{netlist} as the resulting 
\VHDL\ resembles an actual netlist description and not idiomatic \VHDL.

\section{Use cases}
\label{sec:usecases}
\subsection{FIR Filter}
As an example of a common hardware design where the use of higher-order
functions leads to a very natural description is a \acro{FIR} filter, which is 
basically the dot-product of two vectors:

\begin{equation}
y_t  = \sum\nolimits_{i = 0}^{n - 1} {x_{t - i}  \cdot h_i } 
\end{equation}

A \acro{FIR} filter multiplies fixed constants ($h$) with the current 
and a few previous input samples ($x$). Each of these multiplications
are summed, to produce the result at time $t$. The equation of a \acro{FIR} 
filter is indeed equivalent to the equation of the dot-product, which is 
shown below:

\begin{equation}
\mathbf{a}\bullet\mathbf{b} = \sum\nolimits_{i = 0}^{n - 1} {a_i \cdot b_i } 
\end{equation}

We can easily and directly implement the equation for the dot-product
using higher-order functions:

\begin{code}
as *+* bs = foldl1 (+) (zipWith (*) as bs)
\end{code}

The \hs{zipWith} function is very similar to the \hs{map} function seen 
earlier: It takes a function, two vectors, and then applies the function to 
each of the elements in the two vectors pairwise (\emph{e.g.}, \hs{zipWith (*) 
[1, 2] [3, 4]} becomes \hs{[1 * 3, 2 * 4]}).

The \hs{foldl1} function takes a binary function, a single vector, and applies 
the function to the first two elements of the vector. It then applies the
function to the result of the first application and the next element in the 
vector. This continues until the end of the vector is reached. The result of 
the \hs{foldl1} function is the result of the last application. It is obvious 
that the \hs{zipWith (*)} function is pairwise multiplication and that the 
\hs{foldl1 (+)} function is summation.
% Returning to the actual \acro{FIR} filter, we will slightly change the 
% equation describing it, so as to make the translation to code more obvious and 
% concise. What we do is change the definition of the vector of input samples 
% and delay the computation by one sample. Instead of having the input sample 
% received at time $t$ stored in $x_t$, $x_0$ now always stores the newest 
% sample, and $x_i$ stores the $ith$ previous sample. This changes the equation 
% to the following (note that this is completely equivalent to the original 
% equation, just with a different definition of $x$ that will better suit the 
% transformation to code):
% 
% \begin{equation}
% y_t  = \sum\nolimits_{i = 0}^{n - 1} {x_i  \cdot h_i } 
% \end{equation}
The complete definition of the \acro{FIR} filter in code then becomes:

\begin{code}
fir (State (xs,hs)) x = 
  (State (x >> xs,hs), (x +> xs) *+* hs)
\end{code}

Where the vector \hs{xs} contains the previous input samples, the vector \hs{hs} contains the \acro{FIR} coefficients, and \hs{x} is the current input sample. The concatenate operator (\hs{+>}) creates a new vector by placing the current sample (\hs{x}) in front of the previous samples vector (\hs{xs}). The code for the shift (\hs{>>}) operator, that adds the new input sample (\hs{x}) to the list of previous input samples (\hs{xs}) and removes the oldest sample, is shown below:

\begin{code}
x >> xs = x +> init xs  
\end{code}

Where the \hs{init} function returns all but the last element of a vector. 
The resulting netlist of a 4-taps \acro{FIR} filter, created by specializing 
the vectors of the \acro{FIR} code to a length of 4, is depicted in 
\Cref{img:4tapfir}.

\begin{figure}
\centerline{\includegraphics{4tapfir.svg}}
\caption{4-taps \acrotiny{FIR} Filter}
\label{img:4tapfir}
\end{figure}

\subsection{Higher-order CPU}
The following simple CPU is an example of user-defined higher order
functions and pattern matching. The CPU consists of four function units,
of which three have a fixed function and one can perform some less
common operations.

The CPU contains a number of data sources, represented by the horizontal
lines in figure TODO:REF. These data sources offer the previous outputs
of each function units, along with the single data input the cpu has and
two fixed intialization values.

Each of the function units has both its operands connected to all data
sources, and can be programmed to select any data source for either
operand. In addition, the leftmost function unit has an additional
opcode input to select the operation it performs. Its output is also the
output of the entire cpu.

Looking at the code, the function unit is the most simple. It arranges
the operand selection for the function unit. Note that it does not
define the actual operation that takes place inside the function unit,
but simply accepts the (higher order) argument \hs{op} which is a function
of two arguments that defines the operation.

\begin{code}
fu op inputs (addr1, addr2) = regIn
  where
    in1     = inputs!addr1
    in2     = inputs!addr2
    regIn   = op in1 in2
\end{code}

The multiop function defines the operation that takes place in the
leftmost function unit. It is essentially a simple three operation alu
that makes good use of pattern matching and guards in its description.
The \hs{shift} function used here shifts its first operand by the number
of bits indicated in the second operand, the \hs{xor} function produces
the bitwise xor of its operands.

\begin{code}
data Opcode = Shift | Xor | Equal

multiop :: Opcode -> Word -> Word -> Word
multiop opc a b = case opc of
  Shift             -> shift a b
  Xor               -> xor a b 
  Equal | a == b    -> 1
        | otherwise -> 0
\end{code}

The cpu function ties everything together. It applies the \hs{fu}
function four times, to create a different function unit each time. The
first application is interesting, because it does not just pass a
function to \hs{fu}, but a partial application of \hs{multiop}. This
shows how the first funcition unit effectively gets an extra input,
compared to the others.

The vector \hs{inputs} is the set of data sources, which is passed to
each function unit for operand selection. The cpu also receives a vector
of address pairs, which are used by each function unit to select their
operand. The application of the function units to the \hs{inputs} and
\hs{addrs} arguments seems quite repetive and could be rewritten to use
a combination of the \hs{map} and \hs{zipwith} functions instead.
However, the prototype does not currently support working with lists of
functions, so the more explicit version of the code is given instead).

\begin{code}
type CpuState = State [Word | 4]

cpu :: CpuState -> Word -> [(Index 6, Index 6) | 4] 
       -> Opcode -> (CpuState, Word)
cpu (State s) input addrs opc = (State s', out)
  where
    s'    =   [ fu (multiop opc)  inputs (addrs!0)
              , fu add            inputs (addrs!1)
              , fu sub            inputs (addrs!2)
              , fu mul            inputs (addrs!3)
              ]
    inputs    =   0 +> (1 +> (input +> s))
    out       =   head s'
\end{code}

Of course, this is still a simple example, but it could form the basis
of an actual design, in which the same techniques can be reused.

\section{Related work}
This section describes the features of existing (functional) hardware 
description languages and highlights the advantages that this research has 
over existing work.

Many functional hardware description languages have been developed over the 
years. Early work includes such languages as $\mu$\acro{FP}~\cite{muFP}, an 
extension of Backus' \acro{FP} language to synchronous streams, designed 
particularly for describing and reasoning about regular circuits. The 
Ruby~\cite{Ruby} language uses relations, instead of functions, to describe 
circuits, and has a particular focus on layout. 

\acro{HML}~\cite{HML2} is a hardware modeling language based on the strict 
functional language \acro{ML}, and has support for polymorphic types and 
higher-order functions. Published work suggests that there is no direct 
simulation support for \acro{HML}, but that a description in \acro{HML} has to 
be translated to \VHDL\ and that the translated description can then be 
simulated in a \VHDL\ simulator. Also not all of the mentioned language 
features of \acro{HML} could be translated to hardware. The \CLaSH\ compiler 
on the other hand can correctly translate all of the language constructs 
mentioned in this paper to a netlist format.

Like the work presented in this paper, many functional hardware description languages have some sort of foundation in the functional programming language Haskell. Hawk~\cite{Hawk1} uses Haskell to describe system-level executable 
specifications used to model the behavior of superscalar microprocessors. Hawk 
specifications can be simulated; to the best knowledge of the authors there is however no support for automated circuit synthesis. 

The ForSyDe~\cite{ForSyDe2} system uses Haskell to specify abstract system 
models, which can (manually) be transformed into an implementation model using 
semantic preserving transformations. A designer can model systems using 
heterogeneous models of computation, which include continuous time, 
synchronous and untimed models of computation. Using so-called domain 
interfaces a designer can simulate electronic systems which have both analog 
as digital parts. ForSyDe has several backends including simulation and 
automated synthesis, though automated synthesis is restricted to the 
synchronous model of computation within ForSyDe. Unlike \CLaSH\ there is no 
support for the automated synthesis of descriptions that contain polymorphism 
or higher-order functions.

Lava~\cite{Lava} is a hardware description language that focuses on the 
structural representation of hardware. Besides support for simulation and 
circuit synthesis, Lava descriptions can be interfaced with formal method 
tools for formal verification. Lava descriptions are actually circuit 
generators when viewed from a synthesis viewpoint, in that the language 
elements of Haskell, such as choice, can be used to guide the circuit 
generation. If a developer wants to insert a choice element inside an actual 
circuit he will have to explicitly instantiate a multiplexer-like component. 
In this respect \CLaSH\ differs from Lava, in that all the choice elements, 
such as case-statements and pattern matching, are synthesized to choice 
elements in the eventual circuit. As such, richer control structures can both 
be specified and synthesized in \CLaSH\ compared to any of the embedded 
languages such as Hawk, ForSyDe and Lava.

The merits of polymorphic typing, combined with higher-order functions, are 
now also recognized in the `main-stream' hardware description languages, 
exemplified by the new \VHDL-2008 standard~\cite{VHDL2008}. \VHDL-2008 support 
for generics has been extended to types and subprograms, allowing a developer 
to describe components with polymorphic ports and function-valued arguments. 
Note that the types and subprograms still require an explicit generic map, 
whereas types can be automatically inferred, and function-values can be 
automatically propagated by the \CLaSH\ compiler. There are also no (generally 
available) \VHDL\ synthesis tools that currently support the \VHDL-2008 
standard, and thus the synthesis of polymorphic types and function-valued 
arguments.

% Wired~\cite{Wired},, T-Ruby~\cite{T-Ruby}, Hydra~\cite{Hydra}. 
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\section{Conclusion}
This research demonstrates once more that functional languages are well suited 
for hardware descriptions: function applications provide an elegant notation 
for component instantiation. Where this research goes beyond the existing 
(functional) hardware descriptions languages is the inclusion of various 
choice elements, such as patter matching, that are well suited to describe the 
conditional assignments in control-oriented hardware. Besides being able to 
translate these basic constructs to synthesizable \VHDL, the prototype 
compiler can also correctly translate descriptions that contain both 
polymorphic types and function-valued arguments.

Where recent functional hardware description languages have mostly opted to 
embed themselves in an existing functional language, this research features a 
`true' compiler. As a result there is a clear distinction between compile-time 
and run-time, which allows a myriad of choice constructs to be part of the 
actual circuit description; a feature the embedded hardware description 
languages do not offer.

\section{Future Work}
The choice of describing state explicitly as extra arguments and results can 
be seen as a mixed blessing. Even though the description that use state are 
usually very clear, one finds that dealing with unpacking, passing, receiving 
and repacking can become tedious and even error-prone, especially in the case 
of sub-states. Removing this boilerplate, or finding a more suitable 
abstraction mechanism would make \CLaSH\ easier to use.

The transformations in normalization phase of the prototype compiler were 
developed in an ad-hoc manner, which makes the existence of many desirable 
properties unclear. Such properties include whether the complete set of 
transformations will always lead to a normal form or if the normalization 
process always terminates. Though various use cases suggests that these 
properties usually hold, they have not been formally proven. A systematic 
approach to defining the set of transformations allows one to proof that the 
earlier mentioned properties do indeed exist.

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