Add a simple four-bit shift register model.

This model is already translatable to VHDL.

diff --git a/Adders.hs b/Adders.hs
index ce261668e48eb7a9afd5a8e05ddb4bd31f65edf0..ac93a3366db359f3fc368467fe7280320aece926 100644 (file)
--- a/Adders.hs
+++ b/Adders.hs
@@ -39,6 +39,14 @@ dff d s = (s', q)
     q = s
     s' = d
 
+type ShifterState = (Bit, Bit, Bit, Bit)
+shifter :: Bit -> ShifterState -> (ShifterState, Bit)
+shifter a s =
+  (s', o)
+  where
+    s' = (a, b, c, d)
+    (b, c, d, o) = s
+
 -- Combinatoric stateless no-carry adder
 -- A -> B -> S
 no_carry_adder :: (Bit, Bit) -> Bit

diff --git a/Translator.hs b/Translator.hs
index c16406be3aef2781484251c56a21d3e5fb394f54..cf2fb966876c5ffd612d00360dfe772a4adf2110 100644 (file)
--- a/Translator.hs
+++ b/Translator.hs
@@ -45,7 +45,7 @@ main = do
   -- Load the module
   core <- loadModule "Adders.hs"
   -- Translate to VHDL
-  vhdl <- moduleToVHDL core ["dff"]
+  vhdl <- moduleToVHDL core ["shifter"]
   -- Write VHDL to file
   writeVHDL vhdl "../vhdl/vhdl/output.vhdl"