Always use a lowercase letter after a colon.

[matthijs/master-project/report.git] / Chapters / Prototype.tex

diff --git a/Chapters/Prototype.tex b/Chapters/Prototype.tex
index b391d4fcbc6951c2c86af451b805cec8187aae28..7d99104629c0ecbe92d76829b30fa0637dc69874 100644 (file)
--- a/Chapters/Prototype.tex
+++ b/Chapters/Prototype.tex
@@ -73,7 +73,7 @@
     Haskell an obvious choice.
 
   \section[sec:prototype:output]{Output format}
     Haskell an obvious choice.
 
   \section[sec:prototype:output]{Output format}

-    The second important question is: What will be our output format?
+    The second important question is: what will be our output format?

     This output format should at least allow for programming the
     hardware design into a field-programmable gate array (\small{FPGA}).
     The choice of output format is thus limited by what hardware
     This output format should at least allow for programming the
     hardware design into a field-programmable gate array (\small{FPGA}).
     The choice of output format is thus limited by what hardware


@@ -379,7 +379,7 @@
       func arg
       \stoplambda
       This is function application. Each application consists of two
       func arg
       \stoplambda
       This is function application. Each application consists of two

-      parts: The function part and the argument part. Applications are used
+      parts: the function part and the argument part. Applications are used

       for normal function \quote{calls}, but also for applying type
       abstractions and data constructors.
 
       for normal function \quote{calls}, but also for applying type
       abstractions and data constructors.
 


@@ -884,7 +884,7 @@
       Word} and \hs{Word} types by pattern matching and by using the explicit
       the \hs{State constructor}.
 
       Word} and \hs{Word} types by pattern matching and by using the explicit
       the \hs{State constructor}.
 

-      This explicit conversion makes the \VHDL\ generation easier: Whenever we
+      This explicit conversion makes the \VHDL\ generation easier: whenever we

       remove (unpack) the \hs{State} type, this means we are accessing the
       current state (\eg, accessing the register output). Whenever we are a
       adding (packing) the \hs{State} type, we are producing a new value for
       remove (unpack) the \hs{State} type, this means we are accessing the
       current state (\eg, accessing the register output). Whenever we are a
       adding (packing) the \hs{State} type, we are producing a new value for


@@ -1246,7 +1246,7 @@
       function.
 
       Fortunately, the \lam{accs'} variable (and any other substate) has a
       function.
 
       Fortunately, the \lam{accs'} variable (and any other substate) has a

-      property that we can easily check: It has a \lam{State} type
+      property that we can easily check: it has a \lam{State} type

       annotation. This means that whenever \VHDL\ is generated for a tuple
       (or other algebraic type), we can simply leave out all elements that
       have a \lam{State} type. This will leave just the parts of the state
       annotation. This means that whenever \VHDL\ is generated for a tuple
       (or other algebraic type), we can simply leave out all elements that
       have a \lam{State} type. This will leave just the parts of the state


@@ -1303,7 +1303,7 @@
       \stoplambda
               
       When we would really leave out the crossed out parts, we get a slightly
       \stoplambda
               
       When we would really leave out the crossed out parts, we get a slightly

-      weird program: There is a variable \lam{s} which has no value, and there
+      weird program: there is a variable \lam{s} which has no value, and there

       is a variable \lam{s'} that is never used. Together, these two will form
       the state process of the function. \lam{s} contains the "current" state,
       \lam{s'} is assigned the "next" state. So, at the end of each clock
       is a variable \lam{s'} that is never used. Together, these two will form
       the state process of the function. \lam{s} contains the "current" state,
       \lam{s'} is assigned the "next" state. So, at the end of each clock