Add generated VHDL to the hardware description chapter.

[matthijs/master-project/report.git] / Chapters / Prototype.tex

diff --git a/Chapters/Prototype.tex b/Chapters/Prototype.tex
index 7adcfcf5c19ef89dfa7eafee67705ef09936960d..390e98b57c39dc0a1da114a812bd4e8272d1967a 100644 (file)
--- a/Chapters/Prototype.tex
+++ b/Chapters/Prototype.tex
@@ -188,7 +188,7 @@
       % Draw the objects (and deferred labels)
       drawObj (inp, front, desugar, simpl, back, out);
     \stopuseMPgraphic
-    \placefigure[right]{GHC compiler pipeline}{\useMPgraphic{ghc-pipeline}}
+    \placefigure[right]{GHC compiler pipeline}{\startboxed \useMPgraphic{ghc-pipeline}\stopboxed}
 
     \startdesc{Frontend}
       This step takes the Haskell source files and parses them into an
@@ -279,7 +279,7 @@
       % Draw the objects (and deferred labels)
       drawObj (inp, front, norm, vhdl, out);
     \stopuseMPgraphic
-    \placefigure[right]{Cλash compiler pipeline}{\useMPgraphic{clash-pipeline}}
+    \placefigure[right]{Cλash compiler pipeline}{\startboxed \useMPgraphic{clash-pipeline}\stopboxed}
 
     \startdesc{Frontend}
       This is exactly the frontend from the \small{GHC} pipeline, that
@@ -902,9 +902,9 @@
       needed. For example, consider the following state type (this is just the
       state type, not the entire function type):
 
-      \starttyping
+      \starthaskell
       State (State Bit, State (State Word, Bit), Word)
-      \stoptyping
+      \stophaskell
 
       We cannot leave all these \hs{State} type constructors out, since that
       would change the type (unlike when using type synonyms). However, when
@@ -1424,11 +1424,11 @@
         end architecture structural;
       \stopbuffer 
     
-      \placeexample[][ex:AvgStateTypes]{\VHDL\ types generated for acc and avg from \in{example}[ex:AvgState]}
+      \placeexample[][ex:AvgStateTypes]{\VHDL\ types generated for \hs{acc} and \hs{avg} from \in{example}[ex:AvgState]}
           {\typebuffervhdl{AvgStateTypes}}
-      \placeexample[][ex:AccStateVHDL]{\VHDL\ generated for acc from \in{example}[ex:AvgState]}
+      \placeexample[][ex:AccStateVHDL]{\VHDL\ generated for \hs{acc} from \in{example}[ex:AvgState]}
           {\typebuffervhdl{AccStateVHDL}}
-      \placeexample[][ex:AvgStateVHDL]{\VHDL\ generated for avg from \in{example}[ex:AvgState]}
+      \placeexample[][ex:AvgStateVHDL]{\VHDL\ generated for \hs{avg} from \in{example}[ex:AvgState]}
           {\typebuffervhdl{AvgStateVHDL}}
 %    \subsection{Initial state}
 %      How to specify the initial state? Cannot be done inside a hardware