Put "VHDL" in small caps everywhere.

[matthijs/master-project/report.git] / Chapters / Prototype.tex

diff --git a/Chapters/Prototype.tex b/Chapters/Prototype.tex
index 9e6893acccee0ff3d319545c78064c8a4365d5ae..293e00451a76c0647b8d58c480e7b7cd1aca9c75 100644 (file)
--- a/Chapters/Prototype.tex
+++ b/Chapters/Prototype.tex
@@ -149,7 +149,7 @@
       newEmptyBox.inp(0,0);
       newBox.front(btex \small{GHC} frontend + desugarer etex);
       newBox.norm(btex Normalization etex);
-      newBox.vhdl(btex VHDL generation etex);
+      newBox.vhdl(btex \small{VHDL} generation etex);
       newEmptyBox.out(0,0);
 
       % Space the boxes evenly
@@ -166,7 +166,7 @@
       ObjLabel.inp(btex Haskell source etex) "labpathname(haskell)", "labdir(rt)";
       ObjLabel.front(btex Core etex) "labpathname(core)", "labdir(rt)";
       ObjLabel.norm(btex Normalized core etex) "labpathname(normal)", "labdir(rt)";
-      ObjLabel.vhdl(btex VHDL description etex) "labpathname(vhdl)", "labdir(rt)";
+      ObjLabel.vhdl(btex \small{VHDL} description etex) "labpathname(vhdl)", "labdir(rt)";
 
       % Draw the objects (and deferred labels)
       drawObj (inp, front, norm, vhdl, out);
@@ -185,9 +185,9 @@
       order expressions, has a specific structure, etc.), but is also very
       close to directly describing hardware.
     \stopdesc
-    \startdesc{VHDL generation}
+    \startdesc{\small{VHDL} generation}
       The last step takes the normal formed core representation and generates
-      VHDL for it. Since the normal form has a specific, hardware-like
+      \small{VHDL} for it. Since the normal form has a specific, hardware-like
       structure, this final step is very straightforward.
     \stopdesc