vendor, or even only with specific chips). This limits the applicability
of our prototype. Also, the tools we would like to use for verifying,
simulating and draw pretty pictures of our output (like Precision, or
QuestaSim) are designed for \small{VHDL} or Verilog input.
For these reasons, we will not use \small{EDIF}, but \small{VHDL} as our
vendor, or even only with specific chips). This limits the applicability
of our prototype. Also, the tools we would like to use for verifying,
simulating and draw pretty pictures of our output (like Precision, or
QuestaSim) are designed for \small{VHDL} or Verilog input.
For these reasons, we will not use \small{EDIF}, but \small{VHDL} as our