Don't suggest messing with the clock input.

[matthijs/master-project/report.git] / Chapters / Normalization.tex

diff --git a/Chapters/Normalization.tex b/Chapters/Normalization.tex
index cbb634c312d72c68872e65274973992260bc9518..5a3fecb802f5833565eefe87df5e9601d910c1a8 100644 (file)
--- a/Chapters/Normalization.tex
+++ b/Chapters/Normalization.tex
@@ -208,11 +208,10 @@
     (like \lam{map}). The graphical version of the architecture contains
     a slightly simplified version, since the state tuple packing and
     unpacking have been left out. Instead, two separate registers are
-    drawn. Also note that most synthesis tools will further optimize
-    this architecture by removing the multiplexers at the register input
-    and instead put some gates in front of the register's clock input,
-    but we want to show the architecture as close to the description as
-    possible.
+    drawn. Most synthesis tools will further optimize this architecture by
+    removing the multiplexers at the register input and instead use the write
+    enable port of the register (when it is available), but we want to show
+    the architecture as close to the description as possible.
 
     As you can see from the previous examples, the generation of the final
     architecture from the normal form is straightforward. In each of the
@@ -1634,7 +1633,10 @@
 
       \subsubsection[sec:normalization:defunctionalization]{Defunctionalization}
         These transformations remove higher-order expressions from our
-        program, making all values first-order.
+        program, making all values first-order. The approach used for
+        defunctionalization uses a combination of specialization, inlining and
+        some cleanup transformations, was also proposed in parallel research
+        by Neil Mitchell \cite[mitchell09].
       
         Higher order values are always introduced by lambda abstractions, none
         of the other Core expression elements can introduce a function type.