-\chapter{Introduction}
+\chapter[chap:introduction]{Introduction}
+\fixme{No chapter number?}
This thesis describes the result and process of my work during my
Master's assignment. In these pages, I will try to introduce the world
of hardware descriptions, the world of functional languages and
-compilers, and present the compiler that will connect these worlds and
-sets a first step towards making hardware programming on the whole
-easier, more maintainable and generally more pleasant.
+compilers and introduce the hardware description language Cλash that will
+connect these worlds and puts a step towards making hardware programming
+on the whole easier, more maintainable and generally more pleasant.
\section{Research goals}
This research started out with the notion that a functional program is very
easy to interpret as a hardware description. A functional program typically
does no assumptions about evaluation order and does not have any side
- effects. This fits hardware nicely, since the evaluation order is simply
- everything in parallel.
+ effects. This fits hardware nicely, since the evaluation order for hardware
+ is simply everything in parallel.
- As a motivating example, consider the following simple functional program:
+ As a motivating example, consider the following simple functional
+ program:\footnote[notfinalsyntax]{Note that this example is not in the final
+ Cλash syntax}
\starttyping
-andword :: [Bit] -> [Bit]
-andword = map not
+notword :: [Bit] -> [Bit]
+notword = map not
\stoptyping
- This is a very natural way to describe a lot of parallel and ports, that
- perform a bitwise and on a bitvector. The architecture described would look
+ This is a very natural way to describe a lot of parallel not ports, that
+ perform a bitwise not on a bitvector. The architecture described would look
like the following:
- \startMPcode
+ \startuseMPgraphic{AndWord}
% Create objects
+ save a, inp, out;
newCircle.inp(btex $\overrightarrow{input}$ etex) "framed(false)";
num := 4;
for i=1 upto num:
drawObj(out);
% Draw a dotted line between the middle operations
ncline(a2)(a3) "linestyle(dashed withdots)", "arrows(-)";
+ \stopuseMPgraphic
+ \useMPgraphic{AndWord}
+ \todo{Float graphic?}
- % Clear everything
- clearObj a;
- clearObj inp;
- clearObj out;
- \stopMPcode
-
- Slightly more complicated is the following incremental summation of values:
+ Slightly more complicated is the following incremental summation of
+ values:\note[notfinalsyntax]
\starttyping
sum :: [Int] -> [Int]
sum = sum' 0
-sum' :: [Int] -> Int -> [Int]
-sum' [] acc = []
-sum' (x:xs) acc = acc' : (sum' xs acc')
+sum' :: Int -> [Int] -> [Int]
+sum' acc [] = []
+sum' acc (x:xs) = acc' : (sum' acc' xs)
where acc' = x + acc
\stoptyping
the recusion, another number from the input vector is added to the
accumulator and each intermediate step returns its result.
- So, this is a nice description of a bunch of sequential adders that produce
+ So, this is a nice description of a series of sequential adders that produce
the incremental sums of a vector of numbers. For an input list of length 4,
this is the corresponding architecture:
for i=1 upto num:
newCircle.a[i](btex + etex);
endfor
- newCircle.out(btex $output$ etex) "framed(false)";
+ newCircle.out(btex $\overrightarrow{output}$ etex) "framed(false)";
% Center the input and output ports vertically, and put them left and right
% resp.
\stopMPcode
Or... is this the description of a single accumulating adder, that will add
- one element of each input each clock cycle? In that case, we would have
- described this architecture:
+ one element of each input each clock cycle and has a reset value of 0? In
+ that case, we would have described this architecture:
\startMPcode
save reg, inp, a, out;
newCircle.a(btex + etex);
newCircle.out(btex $output$ etex) "framed(false)";
- % Punt inp, a and out in one horizontal line, with reg above a
+ % Put inp, a and out in one horizontal line, with reg above a
reg.c-a.c=(0cm, 2cm);
a.c-inp.c=(3cm, 0cm);
out.c-a.c=(3cm, 0cm);
distinction in this research. In the first figure, the recursion in the code
is taken as recursion in space and each recursion step results in a
different piece of hardware, all of which are active simultaneously. In the
- second figuer, the recursion in the code is taken as recursion in time and
+ second figure, the recursion in the code is taken as recursion in time and
each recursion step is executed sequentially, \emph{on the same piece of
hardware}.
- In this research we explore how to apply these two interpretations two
+ In this research we explore how to apply these two interpretations to
hardware descriptions. Additionally, we explore how other functional
programming concepts can be applied to hardware descriptions to give use an
efficient way to describe hardware.
This leads us to the following research question:
+ \todo{Include Haskell in questions?}
% Slightly bigger font, some extra spacing.
\setupquotation[style=tfb,spacebefore=5mm]
How can we describe the structural properties of a hardware design, using
a functional language?
\stopquotation
+ \setupquotation[style=normal,spacebefore=]
We can further split this into subquestions from a hardware perspective:
\startitemize
\item How can we describe (hierarchical) structure in a design?
\stopitemize
- functional perspective:
+ And subquestions from a functional perspective:
\startitemize
\item How to interpret recursion in descriptions?
\item How to interpret polymorphism?
- \item How to interpret higher order in descriptions?
+ \item How to interpret higher order descriptions?
\stopitemize
+ \todo{Introduce Cλash?}
+
+ In addition to looking at designing a hardware description language, we
+ will also implement a prototype to test drive our ideas. This prototype will
+ translate hardware descriptions written in the Haskell functional language
+ to simple (netlist-like) hardware descriptions in the \VHDL language. The
+ reasons for choosing these languages are detailed in section
+ \in{}[sec:prototype:input] and \in{}[sec:prototype:output] respectively.
+
\section{Outline}
+\fxnote{This section needs updating}
In the first chapter, we will sketch the context for this research.
The current state and history of hardware description languages will be
briefly discussed, as well as the state and history of functional
their application are the subject of the fourth chapter.
The final chapter sketches ideas for further research, which are many. Some of
-have seen some initial exploration and could provide a basis for future work
-in this area.
+them have seen some initial exploration and could provide a basis for future
+work in this area.
+
+% vim: set sw=2 sts=2 expandtab:
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