Update outline.

[matthijs/master-project/report.git] / Chapters / Introduction.tex

diff --git a/Chapters/Introduction.tex b/Chapters/Introduction.tex
index 0f0097bc67e3f54c7ac197698abfc79d543f5bfa..595a07485b195b7052e74db5625a8804da9ec5cf 100644 (file)
--- a/Chapters/Introduction.tex
+++ b/Chapters/Introduction.tex
@@ -88,7 +88,7 @@ sum' (x:xs) acc = acc' : (sum' xs acc')
     for i=1 upto num:
       newCircle.a[i](btex + etex);
     endfor 
-    newCircle.out(btex $output$ etex) "framed(false)";
+    newCircle.out(btex $\overrightarrow{output}$ etex) "framed(false)";
 
     % Center the input and output ports vertically, and put them left and right
     % resp.
@@ -185,13 +185,20 @@ sum' (x:xs) acc = acc' : (sum' xs acc')
     \item How can we describe (hierarchical) structure in a design?
   \stopitemize
   
-  functional perspective:
+  And subquestions from a functional perspective:
   \startitemize
     \item How to interpret recursion in descriptions?
     \item How to interpret polymorphism?
     \item How to interpret higher order in descriptions?
   \stopitemize
 
+  In addition to looking at designing a hardware description language, we
+  will also implement a prototype to test drive our ideas. This prototype will
+  translate hardware descriptions written in the Haskell functional language
+  to simple (netlist-like) hardware descriptions in the \VHDL language. The
+  reasons for choosing these languages are detailed in section
+  \in{}[sec:prototype:input] and \in{}[sec:prototype:output] respectively.
+
 \section{Outline}
 
 In the first chapter, we will sketch the context for this research.