Add an intermezzo about the id function.

[matthijs/master-project/report.git] / Chapters / Introduction.tex

diff --git a/Chapters/Introduction.tex b/Chapters/Introduction.tex
index 2f7172dc4a2bbe36a89f1c8796f462e1a3a45562..3b0a5c1ec9c2723f0968ea0956766d563389f958 100644 (file)
--- a/Chapters/Introduction.tex
+++ b/Chapters/Introduction.tex
@@ -65,7 +65,7 @@ advanced types and provides a case study.
     % Draw a dotted line between the middle operations
     ncline(a2)(a3) "linestyle(dashed withdots)", "arrows(-)";
   \stopuseMPgraphic
-  \placeexample[here][ex:AndWord]{Simple architecture that inverts a vector of bits.}
+  \placeexample[][ex:AndWord]{Simple architecture that inverts a vector of bits.}
     \startcombination[2*1]
       {\typebufferlam{AndWord}}{Haskell description of the architecture.}
       {\boxedgraphic{AndWord}}{The architecture described by the Haskell description.}
@@ -148,7 +148,7 @@ advanced types and provides a case study.
 
   Or... is this the description of a single accumulating adder, that will add
   one element of each input each clock cycle and has a reset value of
-  \lam{0}? In
+  {\definedfont[Serif*normalnum]0}? In
   that case, we would have described the architecture show in \in{example}[ex:RecursiveSumAlt]
 
   \startuseMPgraphic{RecursiveSumAlt}
@@ -220,7 +220,7 @@ advanced types and provides a case study.
   In addition to looking at designing a hardware description language, we
   will also implement a prototype to test ideas. This prototype will
   translate hardware descriptions written in the Haskell functional language
-  to simple (netlist-like) hardware descriptions in the \VHDL language. The
+  to simple (netlist-like) hardware descriptions in the \VHDL\ language. The
   reasons for choosing these languages are detailed in section
   \in{}[sec:prototype:input] and \in{}[sec:prototype:output] respectively.