Put CaseInv and PatternInv in the same float.

[matthijs/master-project/report.git] / Chapters / HardwareDescription.tex

diff --git a/Chapters/HardwareDescription.tex b/Chapters/HardwareDescription.tex
index db469c5f0c12b97aaa3a9ddf4aa820f4f9a6d75f..cac03ed6c0de15d13d27e005eaa959b9d446ba2a 100644 (file)
--- a/Chapters/HardwareDescription.tex
+++ b/Chapters/HardwareDescription.tex
@@ -71,8 +71,8 @@
   application and the corresponding architecture.
 
 \startbuffer[And3]
--- | A simple function that returns 
---   conjunction of three bits
+-- A simple function that returns 
+-- conjunction of three bits
 and3 :: Bit -> Bit -> Bit -> Bit
 and3 a b c = and (and a b) c
 \stopbuffer
@@ -108,12 +108,35 @@ and3 a b c = and (and a b) c
     ncline(andb)(out);
   \stopuseMPgraphic
 
+  \startbuffer[And3VHDL]
+    entity and3Component_0 is
+         port (\azMyG2\ : in std_logic;
+               \bzMyI2\ : in std_logic;
+               \czMyK2\ : in std_logic;
+               \foozMySzMyS2\ : out std_logic;
+               clock : in std_logic;
+               resetn : in std_logic);
+    end entity and3Component_0;
+
+
+    architecture structural of and3Component_0 is
+         signal \argzMyMzMyM2\ : std_logic;
+    begin
+         \argzMyMzMyM2\ <= \azMyG2\ and \bzMyI2\;
+
+         \foozMySzMyS2\ <= \argzMyMzMyM2\ and \czMyK2\;
+    end architecture structural;
+  \stopbuffer
+
   \placeexample[][ex:And3]{Simple three input and gate.}
     \startcombination[2*1]
       {\typebufferhs{And3}}{Haskell description using function applications.}
       {\boxedgraphic{And3}}{The architecture described by the Haskell description.}
     \stopcombination
 
+  \placeexample[][ex:And3VHDL]{\VHDL\ generated for \hs{and3} from \in{example}[ex:And3]}
+      {\typebuffervhdl{And3VHDL}}
+
   \placeintermezzo{}{
     \defref{top level binder}
     \defref{top level function}
@@ -230,7 +253,13 @@ and3 a b c = and (and a b) c
       False -> True
     \stopbuffer
 
-    \startuseMPgraphic{CaseInv}
+    \startbuffer[PatternInv]
+    inv :: Bool -> Bool
+    inv True = False
+    inv False = True
+    \stopbuffer
+
+    \startuseMPgraphic{Inv}
       save in, truecmp, falseout, trueout, out, cmp, mux;
 
       % I/O ports
@@ -263,22 +292,51 @@ and3 a b c = and (and a b) c
       ncline(trueout)(mux) "posB(inpb)";
       ncline(mux)(out) "posA(out)";
     \stopuseMPgraphic
-
-    \placeexample[][ex:CaseInv]{Simple inverter.}
-      \startcombination[2*1]
-        {\typebufferhs{CaseInv}}{Haskell description using a Case expression.}
-        {\boxedgraphic{CaseInv}}{The architecture described by the Haskell description.}
-      \stopcombination
-
-    \startbuffer[PatternInv]
-    inv :: Bool -> Bool
-    inv True = False
-    inv False = True
+    
+    \startbuffer[InvVHDL]
+      entity invComponent_0 is
+           port (\xzAMo2\ : in boolean;
+                 \reszAMuzAMu2\ : out boolean;
+                 clock : in std_logic;
+                 resetn : in std_logic);
+      end entity invComponent_0;
+
+
+      architecture structural of invComponent_0 is
+      begin
+           \reszAMuzAMu2\ <= false when \xzAMo2\ = true else
+                             true;
+      end architecture structural; 
     \stopbuffer
 
-    \placeexample[][ex:PatternInv]{Simple inverter using pattern matching.
-    Describes the same architecture as \in{example}[ex:CaseInv].}
-        {\typebufferhs{PatternInv}}
+    \placeexample[][ex:Inv]{Simple inverter.}{
+      % Use placesidebyside, since nesting combinations doesn't seem to work
+      % here. This does break centering, but well...
+      \placesidebyside
+        % Use 2*2 instead of 1*2 to insert some extra space (\placesidebyside
+        % places stuff very close together)
+        {\startcombination[2*2]
+          {\typebufferhs{CaseInv}}{Haskell description using a Case expression.}
+          {}{}
+          {\typebufferhs{PatternInv}}{Haskell description using Pattern matching expression.}
+          {}{}
+        \stopcombination}
+        % Use a 1*1 combination to add a caption
+        {\startcombination[1*1]
+          {\boxedgraphic{Inv}}{The architecture described by the Haskell descriptions.}
+        \stopcombination}
+      }
+
+%    \placeexample[][ex:Inv]{Simple inverter.}{
+%        \startcombination[2*2]
+%          {\typebufferhs{CaseInv}}{Haskell description using a Case expression.}
+%          {}{}
+%          {\typebufferhs{PatternInv}}{Haskell description using Pattern matching expression.}
+%          {\boxedgraphic{Inv}}{The architecture described by the Haskell description.}
+%        \stopcombination
+%    }
+    \placeexample[][ex:InvVHDL]{\VHDL\ generated for \hs{inv} from \in{example}[ex:Inv]}
+        {\typebuffervhdl{InvVHDL}}
 
   \section{Types}
     Translation of two most basic functional concepts has been
@@ -539,7 +597,7 @@ and3 a b c = and (and a b) c
   and the corresponding architecture.
 
 \startbuffer[Quadruple]
--- | Multiply the input word by four.
+-- Multiply the input word by four.
 quadruple :: Word -> Word
 quadruple n = mul (mul n)
   where