Initial import
authorChristiaan Baaij <christiaan.baaij@gmail.com>
Tue, 25 Aug 2009 10:24:22 +0000 (12:24 +0200)
committerChristiaan Baaij <christiaan.baaij@gmail.com>
Tue, 25 Aug 2009 10:24:22 +0000 (12:24 +0200)
12 files changed:
.latexmkrc [new file with mode: 0644]
Makefile [new file with mode: 0644]
PolyAlu.lhs [new file with mode: 0644]
clash-haskell09.lhs [new file with mode: 0644]
demo.lhs [new file with mode: 0644]
howdoesitwork.lhs [new file with mode: 0644]
introduction.lhs [new file with mode: 0644]
mealymachine.svg [new file with mode: 0644]
preamble.tex [new file with mode: 0644]
reducer.lhs [new file with mode: 0644]
summery.lhs [new file with mode: 0644]
talk.fmt [new file with mode: 0644]

diff --git a/.latexmkrc b/.latexmkrc
new file mode 100644 (file)
index 0000000..f6d4634
--- /dev/null
@@ -0,0 +1,8 @@
+# Includes the default latexmk settings in the caes group
+
+my $caes_latexmkrc=`kpsewhich caes_latexmkrc 2>/dev/null`;
+$caes_latexmkrc =~ s/\n//;
+process_rc_file($caes_latexmkrc);
+
+# Add your own settings below
+$pdflatex = 'xelatex -shell-escape -synctex=1 -output-driver="xdvipdfmx -q -E" %O %S';
diff --git a/Makefile b/Makefile
new file mode 100644 (file)
index 0000000..e52a905
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,48 @@
+FILE           = clash-haskell09
+LHS2TEX = lhs2TeX -v --poly --haskell
+LATEXMK = latexmk
+RM                     = rm -f
+RSVG    = rsvg-convert --format=pdf
+
+LHSRCS = \
+       introduction.lhs \
+       PolyAlu.lhs \
+       reducer.lhs \
+       howdoesitwork.lhs \
+       demo.lhs \
+       summery.lhs
+
+LHFORMATS = \
+       talk.fmt
+       
+TEXSRCS = \
+  preamble.tex
+
+SVGFIGURES = \
+  mealymachine.svg
+
+default: clash-haskell09
+
+clash-haskell09: texs figs $(TEXSRCS) $(LHFORMATS)
+       $(LHS2TEX) $(FILE).lhs > $(FILE).tex; \
+       $(LATEXMK) $(FILE); \
+       open $(FILE).pdf; \
+       $(RM) $(LHSRCS:.lhs=.tex)
+
+texs : $(LHSRCS:.lhs=.tex) 
+%.tex : %.lhs
+       $(LHS2TEX) $< > $@
+
+figs : $(SVGFIGURES:.svg=.pdf)
+%.pdf : %.svg
+       $(RSVG) $< > $@
+
+clean:
+               latexmk -CA clash-haskell09
+               $(RM) $(SVGFIGURES:.svg=.pdf)
+               $(RM) $(FILE).tex
+               $(RM) $(FILE).ptb
+               $(RM) $(FILE).synctex.gz
+               $(RM) $(FILE).nav
+               $(RM) $(FILE).snm
+               $(RM) *.hi *.o *.aux
\ No newline at end of file
diff --git a/PolyAlu.lhs b/PolyAlu.lhs
new file mode 100644 (file)
index 0000000..eb97ac3
--- /dev/null
@@ -0,0 +1,115 @@
+%include talk.fmt
+%if style == newcode
+\begin{code}
+{-# LANGUAGE  TypeOperators, TypeFamilies, FlexibleContexts #-}
+module PolyCPU where
+
+import qualified Prelude as P
+\end{code}
+%endif
+
+\section{Polymorphic, Higher-Order CPU}
+\subsection{Introduction}
+\frame
+{
+\frametitle{Small Use Case}
+\begin{itemize}
+  \item Small Polymorphic, Higher-Order CPU
+  \item Each function is turned into a hardware component
+  \item Use of state will be simple
+\end{itemize}
+}
+
+\frame
+{
+\frametitle{Imports}
+\begin{code}
+import {-"{\color<2>[rgb]{1,0,0}"-}CLasH.HardwareTypes{-"}"-}
+import {-"{\color<3>[rgb]{1,0,0}"-}CLasH.Translator.Annotations{-"}"-}
+\end{code}
+}
+
+\subsection{Type Definitions}
+\frame
+{
+First we define some ALU types:
+\begin{code}
+type Op s a         =   a -> {-"{\color<2>[rgb]{1,0,0}"-}Vector s a{-"}"-} -> a
+type Opcode         =   Bit
+\end{code}
+And some Register types:
+\begin{code}
+type RegBank s a    =   {-"{\color<2>[rgb]{1,0,0}"-}Vector (s :+: D1){-"}"-} a
+type RegState s a   =   State (RegBank s a)
+\end{code}
+And a simple Word type:
+\begin{code}
+type Word           =   {-"{\color<3>[rgb]{1,0,0}"-}SizedInt D12{-"}"-}
+\end{code}
+}
+\subsection{Frameworks for Operations}
+\frame
+{
+We make a primitive operation:
+\begin{code}
+primOp :: {-"{\color<2>[rgb]{1,0,0}"-}(a -> a -> a){-"}"-} -> Op s a
+primOp f a b = a `f` a
+\end{code}
+We make a vector operation:
+\begin{code}
+vectOp :: {-"{\color<2>[rgb]{1,0,0}"-}(a -> a -> a){-"}"-} -> Op s a
+vectOp f a b = {-"{\color<2>[rgb]{1,0,0}"-}foldl{-"}"-} f a b
+\end{code}
+}
+\subsection{Polymorphic, Higher-Order ALU}
+\frame
+{
+We define a polymorphic ALU:
+\begin{code}
+alu :: 
+  Op s a -> 
+  Op s a -> 
+  Opcode -> a -> Vector s a -> a
+alu op1 op2 {-"{\color<2>[rgb]{1,0,0}"-}Low{-"}"-}    a b = op1 a b
+alu op1 op2 {-"{\color<2>[rgb]{1,0,0}"-}High{-"}"-}   a b = op2 a b
+\end{code}
+}
+\subsection{Register bank}
+\frame
+{
+Make a simple register bank:
+\begin{code}
+registerBank :: 
+  CXT((NaturalT s ,PositiveT (s :+: D1),((s :+: D1) :>: s) ~ True )) =>
+  (RegState s a) -> a -> {-"{\color<2>[rgb]{1,0,0}"-}RangedWord s{-"}"-} ->
+  {-"{\color<2>[rgb]{1,0,0}"-}RangedWord s{-"}"-} -> Bit -> ((RegState s a), a )
+  
+registerBank (State mem) data_in rdaddr wraddr wrenable = 
+  ((State mem'), data_out)
+  where
+    data_out  =   mem!rdaddr
+    mem'          {-"{\color<3>[rgb]{1,0,0}"-}| wrenable == Low{-"}"-}  = mem
+                  {-"{\color<3>[rgb]{1,0,0}"-}| otherwise{-"}"-}        = replace mem wraddr data_in
+\end{code}
+}
+\subsection{Simple CPU: ALU \& Register Bank}
+\frame
+{
+Combining ALU and register bank:
+\begin{code}
+{-"{\color<2>[rgb]{1,0,0}"-}ANN(actual_cpu TopEntity){-"}"-}
+actual_cpu :: 
+  (Opcode, Word, Vector D4 Word, 
+  RangedWord D9, 
+  RangedWord D9, Bit) -> 
+  RegState D9 Word ->
+  (RegState D9 Word, Word)
+
+actual_cpu (opc, a ,b, rdaddr, wraddr, wren) ram = (ram', alu_out)
+  where
+    alu_out = alu simpleOp vectorOp opc ram_out b
+    (ram',ram_out)  = registerBank ram a rdaddr wraddr wren
+    simpleOp =  primOp  (+)
+    vectorOp =  vectOp  (+)
+\end{code}
+}
diff --git a/clash-haskell09.lhs b/clash-haskell09.lhs
new file mode 100644 (file)
index 0000000..30c4cf3
--- /dev/null
@@ -0,0 +1,27 @@
+\documentclass[hyperref={unicode}]{beamer}
+%include talk.fmt
+\include{preamble}
+
+\title{\clash{}}
+\subtitle{From Haskell To Hardware}
+\author{Christiaan Baaij \& Matthijs Kooijman}
+\institute[University of Twente]
+{
+  Computer Architecture for Embedded Systems \\
+  Faculty of EEMCS \\
+  University of Twente\\
+}
+\date{\today}
+
+\begin{document}
+
+\frame{\titlepage}
+
+\include{introduction}
+\include{PolyAlu}
+\include{reducer}
+\include{howdoesitwork}
+\include{demo}
+\include{summery}
+
+\end{document}
\ No newline at end of file
diff --git a/demo.lhs b/demo.lhs
new file mode 100644 (file)
index 0000000..a887877
--- /dev/null
+++ b/demo.lhs
@@ -0,0 +1,25 @@
+\section{Demonstration}
+
+\frame{
+\frametitle{How do we use \clash{}?}
+As a library:
+\begin{itemize}
+  \item Import the module: CLasH.Translator
+  \item And call \emph{makeVHDLAnnotations ghc\_lib\_dir [files\_to\_translate]}
+\end{itemize}
+Use customized GHC:
+\begin{itemize}
+  \item Call GHC with the --vhdl flag
+  \item Use the :vhdl command in GHCi
+\end{itemize}
+}
+
+\frame{
+\frametitle{Real Demo}
+\begin{itemize}
+  \item We will simulate the small CPU from earlier
+  \item Translate the CPU code to VHDL
+  \item Simulate the generated VHDL
+  \item Synthesize the VHDL to get a hardware schematic
+\end{itemize}
+}
\ No newline at end of file
diff --git a/howdoesitwork.lhs b/howdoesitwork.lhs
new file mode 100644 (file)
index 0000000..39137bd
--- /dev/null
@@ -0,0 +1,15 @@
+%include talk.fmt
+\section{How do you make Hardware from Haskell?}
+\frame
+{
+  \frametitle{So how do you make Hardware from Haskell?}
+  \large{In three simple steps} \pause
+  \begin{itemize}
+    \item No Effort:\\
+    GHC API Parses, Typechecks and Desugars Haskell \pause
+    \item Hard.. sort of: \\
+    Transform resulting Core, GHC's Intermediate Language,\linebreak to a normal form \pause
+    \item Easy: \\
+    Translate Normalized Core to synthesizable VHDL
+  \end{itemize}
+}
\ No newline at end of file
diff --git a/introduction.lhs b/introduction.lhs
new file mode 100644 (file)
index 0000000..d959f8d
--- /dev/null
@@ -0,0 +1,59 @@
+%include talk.fmt
+\section{Introduction}
+\subsection{What will you see}
+\frame
+{
+  \frametitle{What will we see?}
+  \begin{itemize}
+    \item Small tour: what can we describe in \clash{}
+    \item Quick real demo
+  \end{itemize}
+}
+
+\subsection{What is \texorpdfstring{\clash{}}{CLasH}}
+\frame
+{
+  \frametitle{What is \clash{}?}
+  \begin{itemize}
+    \item \clash{}: CAES Language for Hardware Descriptions
+    \item Rapid prototyping language
+    \item Subset of Haskell can be translated to Hardware (VHDL)
+    \item Structural Description of a Mealy Machine
+  \end{itemize}
+}
+\subsection{Mealy Machine}
+\frame
+{
+\frametitle{Mealy Machine}
+  \begin{figure}
+  \centerline{\includegraphics[width=\textwidth]{mealymachine}}
+  \label{img:mealymachine}
+  \end{figure}
+}
+
+\frame
+{
+\frametitle{Haskell Description}
+\begin{code}
+mealyMachine :: 
+  InputSignals ->
+  {-"{\color<2->[rgb]{1,0,0}"-}State{-"}"-} ->
+  (State, OutputSignals)
+mealyMachine inputs {-"{\color<2->[rgb]{1,0,0}"-}state{-"}"-} = ({-"{\color<3->[rgb]{0,0,1}"-}new_state{-"}"-}, output)
+  where
+    {-"{\color<3->[rgb]{0,0,1}"-}new_state{-"}"-}   =   logic     {-"{\color<2->[rgb]{1,0,0}"-}state{-"}"-}   input
+    outputs                                         =   logic     {-"{\color<2->[rgb]{1,0,0}"-}state{-"}"-}   input
+\end{code}
+}
+\subsection{Simulation}
+\frame
+{
+\frametitle{Simulating a Mealy Machine}
+\begin{code}
+run func {-"{\color<2->[rgb]{1,0,0}"-}state{-"}"-} [] = []
+run func {-"{\color<2->[rgb]{1,0,0}"-}state{-"}"-} (i:input) = o:out
+  where
+    ({-"{\color<3->[rgb]{0,0,1}"-}state'{-"}"-}, o) = func {-"{\color<2->[rgb]{1,0,0}"-}state{-"}"-} i
+    out         = run func {-"{\color<3->[rgb]{0,0,1}"-}state'{-"}"-} input
+\end{code}
+}
\ No newline at end of file
diff --git a/mealymachine.svg b/mealymachine.svg
new file mode 100644 (file)
index 0000000..0606504
--- /dev/null
@@ -0,0 +1,270 @@
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+           y="285.46301"
+           x="413.71338"
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+           sodipodi:role="line">Combinatorial</tspan><tspan
+           style="text-align:center;text-anchor:middle"
+           id="tspan2421"
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+         xml:space="preserve"><tspan
+           style="text-align:center;text-anchor:middle"
+           id="tspan2427"
+           y="392.66382"
+           x="413.95752"
+           sodipodi:role="line">Memory</tspan><tspan
+           id="tspan2431"
+           style="text-align:center;text-anchor:middle"
+           y="417.66382"
+           x="413.95752"
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diff --git a/preamble.tex b/preamble.tex
new file mode 100644 (file)
index 0000000..8c730fe
--- /dev/null
@@ -0,0 +1,9 @@
+\mode<presentation>
+{
+  \usetheme{Warsaw}
+  \setbeamercovered{transparent}
+}
+
+\usepackage[english]{babel}
+
+\newcommand{\clash}[0]{C$\lambda$asH}
\ No newline at end of file
diff --git a/reducer.lhs b/reducer.lhs
new file mode 100644 (file)
index 0000000..09013d1
--- /dev/null
@@ -0,0 +1,12 @@
+\section{Real Hardware Designs}
+\frame{
+\frametitle{Is \clash{} usable?}
+\pause
+\begin{itemize}
+  \item It can be used for more than toy examples\pause
+  \item We designed a matrix reduction circuit\pause
+  \item We simulated it in Haskell\pause
+  \item Simulation results in VHDL match\pause
+  \item Synthesis completes without errors or warnings
+\end{itemize}
+}
\ No newline at end of file
diff --git a/summery.lhs b/summery.lhs
new file mode 100644 (file)
index 0000000..2174a0c
--- /dev/null
@@ -0,0 +1,14 @@
+\section{Conclusion}
+
+\frame{
+\frametitle{Some final words}
+\begin{itemize}
+  \item Still a lot to do: make a bigger subset of Haskell translatable
+  \item Real word designs work
+  \item We bring functional expressivity to hardware designs
+\end{itemize}
+}
+
+\frame{
+\centerline{Thank you for listening}
+}
\ No newline at end of file
diff --git a/talk.fmt b/talk.fmt
new file mode 100644 (file)
index 0000000..8d7076a
--- /dev/null
+++ b/talk.fmt
@@ -0,0 +1,18 @@
+%include polycode.fmt
+
+%if style == newcode 
+%format ANN(x) = "{-# ANN " x "#-}"
+%format CXT(x) = "(" x ")"
+%format ^^ = " " 
+%else 
+%format ANN(x) = "\{-\# ANN\ " x " \#-\}"
+%format CXT(x) = "(Some\ context...)" 
+%format ^^ = "\; "
+%format :>:   = "\ensuremath{>}"
+%format :<:   = "\ensuremath{<}"
+%format :==:  = "\ensuremath{\equiv}"
+%format :-:   = "\ensuremath{-}"
+%format :+:   = "\ensuremath{+}"
+%format :*:   = "\ensuremath{*}"
+%format :<=:  = "\ensuremath{\leq}"
+%endif 
\ No newline at end of file