Hopefully finalized presentation
authorChristiaan Baaij <christiaan.baaij@gmail.com>
Mon, 31 Aug 2009 19:55:21 +0000 (21:55 +0200)
committerChristiaan Baaij <christiaan.baaij@gmail.com>
Mon, 31 Aug 2009 19:55:21 +0000 (21:55 +0200)
PolyAlu.lhs
beamerinnerthemecaes.sty
demo.lhs
howdoesitwork.lhs
introduction.lhs
reducer.lhs
reducer.svg
summary.lhs

index c0d196d01d4d0137b1b71aebf824ffd50cc45560..a4dc6e141cce0b0f0314bfae51ce48f81be3f5ba 100644 (file)
@@ -21,6 +21,7 @@ import qualified Prelude as P
 \includegraphics[width=4.75cm]{simpleCPU}
 \end{figure}
 \column{0.5\textwidth}
 \includegraphics[width=4.75cm]{simpleCPU}
 \end{figure}
 \column{0.5\textwidth}
+\vspace{5em}
 \begin{itemize}
   \item Polymorphic, Higher-Order CPU
   \item Use of state will be simple
 \begin{itemize}
   \item Polymorphic, Higher-Order CPU
   \item Use of state will be simple
@@ -49,9 +50,10 @@ First we define some ALU types:
 \begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox}
 \begin{code}
 type Op a         =   a -> a -> a
 \begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox}
 \begin{code}
 type Op a         =   a -> a -> a
+type Opcode       =   Bit
 \end{code}
 \end{beamercolorbox}\pause
 \end{code}
 \end{beamercolorbox}\pause
-\vspace{2.5em}
+\vspace{1em}
 And some Register types:
 \begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox}
 \begin{code}
 And some Register types:
 \begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox}
 \begin{code}
@@ -68,7 +70,8 @@ type Word = SizedInt D12
 %endif
 \end{columns}
 }\note[itemize]{
 %endif
 \end{columns}
 }\note[itemize]{
-\item The first type is already polymorphic in input / output type
+\item The ALU operation is already polymorphic in input / output type
+\item We use a fixed size vector as the placeholder for the registers
 \item State has to be of the State type to be recognized as such
 }
 
 \item State has to be of the State type to be recognized as such
 }
 
@@ -82,7 +85,6 @@ type Word = SizedInt D12
 Abstract ALU definition:
 \begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox}
 \begin{code}
 Abstract ALU definition:
 \begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox}
 \begin{code}
-type Opcode         =   Bit
 alu :: 
   Op a -> Op a -> 
   Opcode -> a -> a -> a
 alu :: 
   Op a -> Op a -> 
   Opcode -> a -> a -> a
@@ -92,7 +94,7 @@ alu op1 op2 {-"{\color<2>[rgb]{1,0,0}"-}High{-"}"-}   a b = op2 a b
 \end{beamercolorbox}
 }\note[itemize]{
 \item Alu is both higher-order, and polymorphic
 \end{beamercolorbox}
 }\note[itemize]{
 \item Alu is both higher-order, and polymorphic
-\item Two parameters are "compile time", others are "runtime"
+\item First two parameters are "compile time", other three are "runtime"
 \item We support pattern matching
 }
 
 \item We support pattern matching
 }
 
@@ -121,10 +123,8 @@ registers data_in rdaddr wraddr (State mem) =
 \end{code}
 \end{beamercolorbox}
 }\note[itemize]{
 \end{code}
 \end{beamercolorbox}
 }\note[itemize]{
-\item RangedWord runs from 0 to the upper bound
-\item mem is statefull
-\item We support guards
-\item replace is a builtin function
+\item mem is statefull, indicated by the 'State' type
+\item replace and (!) are a builtin functions
 }
 
 \subsection{Simple CPU: ALU \& Register Bank}
 }
 
 \subsection{Simple CPU: ALU \& Register Bank}
@@ -155,7 +155,7 @@ cpu (opc, d, rdaddr, wraddr) ram = (ram', alu_out)
 \end{itemize}
 }\note[itemize]{
 \item We use the new Annotion functionality to indicate this is the top level. TopEntity is defined by us.
 \end{itemize}
 }\note[itemize]{
 \item We use the new Annotion functionality to indicate this is the top level. TopEntity is defined by us.
-\item the primOp and vectOp frameworks are now supplied with real functionality, the plus (+) operations
+\item At this stage, both operations for the ALU are defined
 \item No polymorphism or higher-order stuff is allowed at this level.
 \item Functions must be specialized, and have primitives for input and output 
 }
 \item No polymorphism or higher-order stuff is allowed at this level.
 \item Functions must be specialized, and have primitives for input and output 
 }
index 580fe3c1a9d39824afb4a8209fec0af3c5ccd905..29126b7a194cef082e9a253c7b92e29eb8c847a5 100644 (file)
@@ -60,7 +60,7 @@
 \setbeamertemplate{title page}
 {
        \begin{centering}
 \setbeamertemplate{title page}
 {
        \begin{centering}
-    \vfill
+    \vskip2em%
     \begin{beamercolorbox}[sep=8pt,center]{title}
       \usebeamerfont{title}\inserttitle\par%
       \ifx\insertsubtitle\@empty%
     \begin{beamercolorbox}[sep=8pt,center]{title}
       \usebeamerfont{title}\inserttitle\par%
       \ifx\insertsubtitle\@empty%
index 61a55678c9e5bab745a67157955139fe3dfb9dfd..f50a9590df95d6e92a458b5e83aee2d2e49fd44f 100644 (file)
--- a/demo.lhs
+++ b/demo.lhs
@@ -3,6 +3,7 @@
 \frame{
 \frametitle{Demo}
 \begin{itemize}
 \frame{
 \frametitle{Demo}
 \begin{itemize}
+  \item Pre-Recored Video: VHDL Synthesis takes too long
   \item Simulate the CPU description
   \item Translate the CPU to VHDL
   \item Simulate the generated VHDL
   \item Simulate the CPU description
   \item Translate the CPU to VHDL
   \item Simulate the generated VHDL
@@ -14,9 +15,9 @@
 \frame{
 \frametitle{Generated Schematic}
 \begin{figure}
 \frame{
 \frametitle{Generated Schematic}
 \begin{figure}
-\centerline{\includegraphics<1>[width=10cm]{cpucomplete}
-\includegraphics<2>[width=10cm]{cpualu}
-\includegraphics<3>[height=6cm]{cpuregisters}}
+\centerline{\includegraphics<1>[width=10.3cm]{cpucomplete}
+\includegraphics<2>[width=11.3cm]{cpualu}
+\includegraphics<3>[height=6.3cm]{cpuregisters}}
 \end{figure}
 }
 
 \end{figure}
 }
 
index b9970d6784d570e7d2e1863be8c4b2e0fe064901..4c26ca534ffecfa49b9e7362b68d2f0c985316c6 100644 (file)
@@ -14,7 +14,8 @@
   \end{itemize}
 }\note[itemize]{
 \item Here is a quick insight as to how WE translate Haskell to Hardware
   \end{itemize}
 }\note[itemize]{
 \item Here is a quick insight as to how WE translate Haskell to Hardware
+\item Reduction rules are used to get a required normal form.
 \item Normal form already looks like hardware (components and lines)
 \item Normal form already looks like hardware (components and lines)
-\item You can also use TH, like ForSyDe. Or traverse datastructures, like ?
+\item You can also use TH, like ForSyDe. Or traverse datastructures, like Lava?
 \item We're in luck with the GHC API update of 6.10 and onwards
 }
 \item We're in luck with the GHC API update of 6.10 and onwards
 }
index c7b0bca887d2cd4873a66393c3253dd86c5f8a13..939582f567348bf2323354e7a58649e7ab76b394 100644 (file)
 \item \clash{} is currently meant for rapid prototyping, not verification of hardware designs
 \item Functional languages are close to Hardware
 \item We can only translate a subset of Haskell
 \item \clash{} is currently meant for rapid prototyping, not verification of hardware designs
 \item Functional languages are close to Hardware
 \item We can only translate a subset of Haskell
-\item All functions are descriptions of Mealy Machines
+\item All functions are structural descriptions with a Mealy Machines perspective
 }
 
 }
 
-% \subsection{Mealy Machine}
-% \frame
-% {
-% \frametitle{What is a Mealy Machine again?}
-%   \begin{figure}
-%   \centerline{\includegraphics[width=10cm]{mealymachine}}
-%   \label{img:mealymachine}
-%   \end{figure}
-% }
-% \note[itemize]{
-% \item Mealy machine bases its output on current input and previous state
-% \item: TODO: Integrate this slide with the next two. First, show the picture
-% with the mealyMachine type signature (and rename it to "func"). Then, show the
-% run function, without type signature. Focus is on correspondence to the
-% picture.
-% }
-
 \frame
 {
 \frame
 {
-\frametitle{Haskell Description}
+\frametitle{Mealy Machine}
 \begin{figure}
 \centerline{\includegraphics<1>[width=6.25cm]{mealymachine2}
 \includegraphics<2>[width=6.25cm]{mealymachine2-func-red}
 \begin{figure}
 \centerline{\includegraphics<1>[width=6.25cm]{mealymachine2}
 \includegraphics<2>[width=6.25cm]{mealymachine2-func-red}
@@ -49,8 +32,8 @@
 \end{figure}
 \begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox}
 \begin{code}
 \end{figure}
 \begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox}
 \begin{code}
-run func {-"{\color<3>[rgb]{1,0,0}"-}state{-"}"-} [] = []
-run func {-"{\color<3>[rgb]{1,0,0}"-}state{-"}"-} (i:inputs) = o:outputs
+run {-"{\color<2>[rgb]{1,0,0}"-}func{-"}"-} {-"{\color<3>[rgb]{1,0,0}"-}state{-"}"-} [] = []
+run {-"{\color<2>[rgb]{1,0,0}"-}func{-"}"-} {-"{\color<3>[rgb]{1,0,0}"-}state{-"}"-} (i:inputs) = o:outputs
   where
     ({-"{\color<3>[rgb]{1,0,0}"-}state'{-"}"-}, o)  =   {-"{\color<2>[rgb]{1,0,0}"-}func{-"}"-} i {-"{\color<3>[rgb]{1,0,0}"-}state{-"}"-}
     outputs                                         =   run {-"{\color<2>[rgb]{1,0,0}"-}func{-"}"-} {-"{\color<3>[rgb]{1,0,0}"-}state'{-"}"-} input
   where
     ({-"{\color<3>[rgb]{1,0,0}"-}state'{-"}"-}, o)  =   {-"{\color<2>[rgb]{1,0,0}"-}func{-"}"-} i {-"{\color<3>[rgb]{1,0,0}"-}state{-"}"-}
     outputs                                         =   run {-"{\color<2>[rgb]{1,0,0}"-}func{-"}"-} {-"{\color<3>[rgb]{1,0,0}"-}state'{-"}"-} input
@@ -58,8 +41,10 @@ run func {-"{\color<3>[rgb]{1,0,0}"-}state{-"}"-} (i:inputs) = o:outputs
 \end{beamercolorbox}
 }
 \note[itemize]{
 \end{beamercolorbox}
 }
 \note[itemize]{
+\item A Mealy machine bases its output on the current state and the input
 \item State is part of the function signature
 \item State is part of the function signature
-\item Both the current state, as the updated State
+\item Both the current state, and the updated State
+\item The run function simulates a mealy machine for the provided number of inputs
 }
 
 \frame
 }
 
 \frame
@@ -77,3 +62,7 @@ func ::
 \end{code}
 \end{beamercolorbox}
 }
 \end{code}
 \end{beamercolorbox}
 }
+\note[itemize]{
+\item In \clash{} you describe the logic part of the mealy machine
+\item The state in the signature is turned into memory elements when translating to VHDL
+}
index 03c688c520ac496f98c8657ca05968c9c96658d0..21baeeb9db140eb52b071981ba1403677a7b8313 100644 (file)
@@ -10,7 +10,7 @@
 \column{0.5\textwidth}
 \begin{itemize}
   \item We implemented a reduction circuit in \clash{}\pause
 \column{0.5\textwidth}
 \begin{itemize}
   \item We implemented a reduction circuit in \clash{}\pause
-  \item Simulation results in Haskell match VHDL simulation results\pause
+  \item Simulated first Haskell. VHDL simulation results match\pause
   \item Synthesis completes without errors or warnings\pause
   \item Around half speed of handcoded and optimized VHDL
 \end{itemize}
   \item Synthesis completes without errors or warnings\pause
   \item Around half speed of handcoded and optimized VHDL
 \end{itemize}
@@ -18,7 +18,9 @@
 }\note[itemize]{
 \item Toys like the poly cpu one are good to give a quick demo
 \item But we used \clash{} to design 'real' hardware
 }\note[itemize]{
 \item Toys like the poly cpu one are good to give a quick demo
 \item But we used \clash{} to design 'real' hardware
-\item Reduction circuit sums the numbers in a row of a (sparse) matrix
+\item Reduction circuit sums the numbers in a row, of different length
+\item It uses a pipelined adder: multiple rows in pipeline, rows longer than pipeline
+\item We hope you see this is not a trivial problem
 \item Nice speed considering we don't optimize for it (only single example!)
 }
 
 \item Nice speed considering we don't optimize for it (only single example!)
 }
 
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+     style="font-size:20px;font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;text-align:start;line-height:125%;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;font-family:Palatino;-inkscape-font-specification:Palatino"
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+     y="184.33662"
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+     sodipodi:linespacing="125%"><tspan
+       sodipodi:role="line"
+       id="tspan3381"
+       x="62.196404"
+       y="184.33662">Input rows</tspan></text>
+  <path
+     style="fill:none;fill-rule:evenodd;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;marker-start:none;marker-end:url(#Arrow2Lend);stroke-opacity:1"
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+     id="path3391" />
+  <text
+     xml:space="preserve"
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+       style="text-align:center;text-anchor:middle">Pipelined</tspan><tspan
+       sodipodi:role="line"
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+       y="124.68092"
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index 58feaa978ba49d88a41b10fc8f5bdfef080491e5..6467af850bfab988a81e647dae282ac70a23b86d 100644 (file)
@@ -5,8 +5,8 @@
 \frametitle{Some final words}
 \begin{itemize}
   \item Still a lot to do: translate larger subset of Haskell
 \frametitle{Some final words}
 \begin{itemize}
   \item Still a lot to do: translate larger subset of Haskell
-  \item Real world prototypes can be made in \clash{}
-  \item \clash{} is another great example of how to bring functional expressivity to hardware designs
+  \item Real world prototype designs can already be made in \clash{}
+%  \item \clash{} is another great example of how to bring functional expressivity to hardware designs
 \end{itemize}
 }
 
 \end{itemize}
 }
 
@@ -37,3 +37,30 @@ registers ::
   (RegState s a, a )
 \end{code}
 }
   (RegState s a, a )
 \end{code}
 }
+
+\frame
+{
+\frametitle{Supported Functionality}
+\begin{itemize}
+\item Polymorphism
+\item Higher Order Functions
+\item Fixed-Size Vectors (Simulation)
+\item Ranged and Sized Integers (Simulation)
+\item Custom Datatypes
+\item Booleans, Tuples
+\item Pattern Matching
+\item Guards
+\end{itemize}
+}
+
+\frame
+{
+\frametitle{Unsupported Functionality}
+\begin{itemize}
+\item Recursions
+\item Lists (Dynamic Length)
+\item Standard Haskell Types: Integer, Char, etc.
+\item Monads
+\item And much much more...
+\end{itemize}
+}