Laatste wijzigingen

[matthijs/master-project/haskell-symposium-talk.git] / reducer.lhs

diff --git a/reducer.lhs b/reducer.lhs
index 09013d17dd60a4bace43f83060e43c639cbf4b4f..cc6d89fb62cc924c201edc33ef78114cfe1ed4e8 100644 (file)
--- a/reducer.lhs
+++ b/reducer.lhs
@@ -1,12 +1,28 @@
 \section{Real Hardware Designs}
 \frame{
-\frametitle{Is \clash{} usable?}
+\frametitle{More than just toys}
 \pause
 \begin{itemize}
-  \item It can be used for more than toy examples\pause
-  \item We designed a matrix reduction circuit\pause
-  \item We simulated it in Haskell\pause
-  \item Simulation results in VHDL match\pause
-  \item Synthesis completes without errors or warnings
+  \item We designed a reduction circuit in \clash{}\pause
+  \item Simulation results in Haskell match VHDL simulation results\pause
+  \item Synthesis completes without errors or warnings\pause
+  \item For the same Virtex-4 FPGA: \pause
+    \begin{itemize}
+      \item Hand coded VHDL design runs at 200 MHz\pause
+      \item \clash{} design runs at around 85* MHz
+    \end{itemize}
 \end{itemize}
-}
\ No newline at end of file
+\vspace{6em}
+\uncover<7->{\scriptsize{*Guestimate: design synthesized at 105 MHz, but with an Integer datapath instead of a floating point datapath.}}
+}\note[itemize]{
+\item Toys like the poly cpu one are good to give a quick demo
+\item But we used \clash{} to design 'real' hardware
+\item Reduction circuit sums the numbers in a row of a (sparse) matrix
+\item Nice speed considering we don't optimize for it
+}
+
+\begin{frame}[plain] 
+   \begin{centering} 
+      \includegraphics[height=\paperheight]{reducerschematic.png} 
+      \end{centering} 
+\end{frame} 
\ No newline at end of file